the processor keeps a return addresses stack (RAS) which stores the address
and the instruction execution state of the instruction after a function-call
type branch instruction.

Calling a "noreturn" function with normal call instructions (e.g. bl) can
corrupt RAS and causes 100% return misprediction so LLVM should use a
unconditional branch instead. i.e.
mov lr, pc
b _foo
The "mov lr, pc" is issued in order to get proper backtrace.

rdar://8979299

llvm-svn: 151623

llvm-svn: 151622

Reverted r152620 - DSE: Shorten memset when a later store overwrites the start of it.  There were all sorts of buildbot issues

llvm-svn: 151621

llvm-svn: 151620

llvm-svn: 151618

llvm-svn: 151617

llvm-svn: 151615

llvm-svn: 151614

Mac OS X. Patch by Fabian Groffen, with a slight tweak by me.

llvm-svn: 151612

load and store instructions.

llvm-svn: 151611

Don't attempt to extend physreg live ranges across calls.

<rdar://problem/10942095>

llvm-svn: 151610

llvm-svn: 151609

llvm-svn: 151607

When an outgoing call takes more than 2k of arguments on the stack, we
don't allocate that call frame in the prolog, but adjust the stack
pointer immediately before the call instead.

This causes problems with the emergency spill slot because PEI can't
track stack pointer adjustments on the second pass, and if the outgoing
arguments are too big, SP can't be used to reach the emergency spill
slot at all.

Work around these problems by ensuring there is a base or frame pointer
that can be used to access the emergency spill slot.

<rdar://problem/10917166>

llvm-svn: 151604

Add -D option to llvm-nm to dump dynamic symbols.

Patch by David Meyer.

llvm-svn: 151600

llvm-svn: 151599

llvm-svn: 151596

llvm-svn: 151594

This patch adds instruction latencies for the SSE instructions
to the instruction scheduler for the Intel Atom.

llvm-svn: 151590

llvm-svn: 151588

Duncan pointed out that if the alignment isn't explicitly specified, it defaults to the ABI alignment.  Given that, make this code a bit more aggressive in such cases.

llvm-svn: 151584

llvm-svn: 151582

llvm-svn: 151580

llvm-svn: 151578

manifests itself when building LLVM with LTO.
<rdar://problem/10913281>

llvm-svn: 151576

Patch by David Meyer.

llvm-svn: 151575

%S5<def> = COPY %S0<kill>
First clear def map of Q1, etc.

No small test case available.

llvm-svn: 151574

We on the linker to resolve calls to the appropriate BL/BLX instruction
to make interworking function correctly. It uses the symbol in the
relocation to do that, so we need to be careful about being too clever.

To enable this for ARM mode, split the BL/BLX fixup kind off from the
unconditional-branch fixups.

rdar://10927209

llvm-svn: 151571

to make it more widely available.

llvm-svn: 151564

Teach BasicAA about the LLVM IR rules that allow reading past the end of an object given sufficient alignment.  Fixes PR12098.

llvm-svn: 151553

llvm-svn: 151552

http://llvm.org/bugs/show_bug.cgi?id=12089

llvm-svn: 151550

MCize function entry label emission on PowerPC64 properly.

llvm-svn: 151547

rdar://10921670
PR11935

llvm-svn: 151543

llvm-svn: 151540

llvm-svn: 151538

After the SlotIndex slot names were updated, it is possible to apply
stricter checks to live intervals.

Also treat bundles as bags of operands when checking live intervals.

llvm-svn: 151531

thumb instruction.  The PC adjustment is +4 in Thumb mode and +8 in ARM mode.

llvm-svn: 151530

The MIOperands iterator can visit operands on a single instruction, or
all operands in a bundle.  This simplifies code like the register
allocator that treats bundles as a set of operands.

llvm-svn: 151529

Found by valgrind.

llvm-svn: 151525