by operator<< on MachineInstr's, and looking up what register "24" is all of the
time was greatly annoying.

llvm-svn: 11623

Move out of line member functions of MachineBasicBlock to
MachineBasicBlock.cpp.

llvm-svn: 11497

llvm-svn: 11393

Rename SetMachineOperandConst's formal parameters to match other methods here.
Mark some methods as being used only by the SPARC back-end.
Fix a missing-paren bug in OutputValue().

llvm-svn: 11363

MachineBasicBlock. Also change opcode to a short and numImplicitRefs
to an unsigned char so that overall MachineInstr's size stays the
same.

llvm-svn: 11357

llvm-svn: 11348

llvm-svn: 11346

operand of the instruction and thus simplify the register allocation.

llvm-svn: 11124

spilled, A was loaded from its stack location twice. This fixes the bug.

llvm-svn: 11093

    a) remove opIsUse(), opIsDefOnly(), opIsDefAndUse()
    b) add isUse(), isDef()
    c) rename opHiBits32() to isHiBits32(),
              opLoBits32() to isLoBits32(),
              opHiBits64() to isHiBits64(),
              opLoBits64() to isLoBits64().

This results to much more readable code, for example compare
"op.opIsDef() || op.opIsDefAndUse()" to "op.isDef()" a pattern used
very often in the code.

llvm-svn: 10461

llvm-svn: 9903

Header files will be on the way.

llvm-svn: 9298

llvm-svn: 8588

llvm-svn: 7675

llvm-svn: 7617

so get rid of the def/use parameters that were getting passed in.

**** This now changes the semantics of these methods to preserve the flags,
     not clobber them!

llvm-svn: 7602

llvm-svn: 7534

llvm-svn: 7531

which args can be substituted: defsOnly, defsAndUses or usesOnly.

llvm-svn: 7154

llvm-svn: 6468

    Fixed spilling of %fcc[0-3] which are part of %fsr.

(2) Moved some machine-independent reg-class code to class TargetRegInfo
    from SparcReg{Class,}Info.

(3) Renamed MachienOperand::opIsDef to MachineOperand::opIsDefOnly()
    and related functions and flags.  Fixed several bugs where only
    "isDef" was being checked, not "isDefAndUse".

llvm-svn: 6341

llvm-svn: 5301

llvm-svn: 5272

llvm-svn: 5217

llvm-svn: 5194

llvm-svn: 5053

llvm-svn: 4737

llvm-svn: 4719

llvm-svn: 4447

llvm-svn: 4446

llvm-svn: 4438

llvm-svn: 4435

llvm-svn: 4426

instead record them as extra operands in the operands[] vector.
Also, move CallArgsDescriptor into this class instead of making it an
annotation on the machine instruction.

llvm-svn: 4399

MachineInstr.cpp

llvm-svn: 4392

llvm-svn: 4389

llvm-svn: 4359

llvm-svn: 4358

llvm-svn: 4357

  by MachineInstr.
* Add a bunch of new methods to allow incremental addition of operands to the
  machine instr instance.

llvm-svn: 4356