Fix disassembler handling of CRC32 which is an odd instruction that uses 0xf2 as an opcode extension and allows the opsize prefix. This necessitated adding IC_XD_OPSIZE and IC_64BIT_XD_OPSIZE contexts. Unfortunately, this increases the size of the disassembler tables. Fixes PR10702.

llvm-svn: 140954

Build on previous patches to successfully distinguish between an M-series and A/R-series MSR and MRS instruction. These take different mask names and have a *slightly* different opcode format.

Add decoder and disassembler tests.

Improvement on the previous patch - successfully distinguish between valid v6m and v7m masks (one is a subset of the other). The patch had to be edited slightly to apply to ToT.

llvm-svn: 140696

llvm-svn: 140579

llvm-svn: 140515

llvm-svn: 140423

Post-index loads/stores in still need to print the post-indexed immediate, even if it's zero, to distinguish them from non-post-indexed instructions.

llvm-svn: 140420

llvm-svn: 140415

llvm-svn: 140370

Fix register printing in disassembling of push/pop of segment registers and in/out in Intel syntax mode. Fixes PR10960

llvm-svn: 140299

Print out immediate offset versions of PC-relative load/store instructions as [pc, #123] rather than simply #123.

llvm-svn: 140283

llvm-svn: 140152

Handle STRT (and friends) like LDRT (and friends) for decoding purposes.  Port over additional encoding tests to decoding tests.

llvm-svn: 140032

llvm-svn: 139970

llvm-svn: 139964

llvm-svn: 139958

llvm-svn: 139943

llvm-svn: 139915

llvm-svn: 139912

Fix mem type for VEX.128 form of VROUNDP*. Remove filter preventing VROUND from being recognized by disassembler.

llvm-svn: 139691

llvm-svn: 139690

llvm-svn: 139689

llvm-svn: 139645

llvm-svn: 139639

Remove filter that was preventing MOVDQU/MOVDQA and their VEX forms from being disassembled. Also added encodings for the other register/register form of these instructions. Fixes PR10848.

llvm-svn: 139588

llvm-svn: 139542

Port more encoding tests to decoding tests, and correct an improper Thumb2 pre-indexed load decoding this uncovered.

llvm-svn: 139522

Fix disassembling of one of the register/register forms of MOVUPS/MOVUPD/MOVAPS/MOVAPD/MOVSS/MOVSD and their VEX equivalents. Fixes PR10877.

llvm-svn: 139486

llvm-svn: 139485

Fix disassembling of PAUSE instruction. Fixes PR10900. Also fixed NOP disassembling to ignore OpSize and REX.W.

llvm-svn: 139484

llvm-svn: 139432

llvm-svn: 139422

llvm-svn: 139356

llvm-svn: 139328

Refactor operand handling for STRD as well. Tests for that forthcoming.

llvm-svn: 139322

llvm-svn: 139256

Second of a three-patch series aiming to fix MSR/MRS on Cortex-M. This adds predicate checking to the Disassembler.

llvm-svn: 139250

llvm-svn: 139244

llvm-svn: 139240

llvm-svn: 139171

case those instructions that the immediate is not sign-extend.  radr://8795217

llvm-svn: 139028