llvm-svn: 110649

Refactor and simplify code to avoid redundant checks.

llvm-svn: 110642

register at a time. This turns out to be slightly faster than iterating over
instructions, but more importantly, it allows us to compute spill weights for
new registers created after the spill weight pass has run.

Also compute the allocation hint at the same time as the spill weight. This
allows us to use the spill weight as a cost metric for copies, and choose the
most profitable hint if there is more than one possibility.

The new hints provide a very small (< 0.1%) but universal code size improvement.

llvm-svn: 110631

pass. This pass should expand with all of the small, fine-grained optimization
passes to reduce compile time and increase happiment.

llvm-svn: 110627

llvm-svn: 110623

llvm-svn: 110621

llvm-svn: 110607

llvm-svn: 110600

llvm-svn: 110590

If we are emitting COPY instructions for the REG_SEQUENCE, make sure the kill
flag goes on the last COPY. Otherwise we may be using a killed register.

<rdar://problem/8287792>

llvm-svn: 110589

llvm-svn: 110586

relatively expensive comparison analyzer on each instruction. Also rename the
comparison analyzer method to something more in line with what it actually does.

This pass is will eventually be folded into the Machine CSE pass.

llvm-svn: 110539

out of PassManager.cpp and into Core.cpp with the rest of the C binding code.

llvm-svn: 110494

necessary.

Sometimes, live range splitting doesn't shrink the current interval, but simply
changes some instructions to use a new interval. That makes the original more
suitable for spilling. In this case, we don't need to duplicate the original.

llvm-svn: 110481

llvm-svn: 110466

llvm-svn: 110464

After heavy editing of a live interval, it is much easier to simply renumber the
live values instead of trying to keep track of the unused ones.

llvm-svn: 110463

llvm-svn: 110460

llvm-svn: 110454

llvm-svn: 110453

When a physical register is in use, some alias of that register has a live
interval with a relevant live range. That is the sad state of intervals after
physreg coalescing of subregs, and it is good enough for correct register
allocation.

llvm-svn: 110452

llvm-svn: 110429

This pass tries to remove comparison instructions when possible. For instance,
if you have this code:

   sub r1, 1
   cmp r1, 0
   bz  L1

and "sub" either sets the same flag as the "cmp" instruction or could be
converted to set the same flag, then we can eliminate the "cmp" instruction all
together. This is a important for ARM where the ALU instructions could set the
CPSR flag, but need a special suffix ('s') to do so.

llvm-svn: 110423

While emitting DBG_VALUE for registers spilled at the end of a block do not use location of MBB->end(). If a block does not have terminator then incoming iterator points to end().

llvm-svn: 110411

llvm-svn: 110410

When a joined COPY changes subreg liveness, we keep it around as a KILL,
otherwise it is safe to delete.

llvm-svn: 110403

LiveVariables becomes horribly wrong while the coalescer is running, but the
analysis is not zapped until after the coalescer pass has run. This causes tons
of false reports when calling verify form the coalescer.

llvm-svn: 110402

ID member as the sole unique type identifier.  Clean up APIs related to this change.

llvm-svn: 110396

We verify that the LiveInterval is live at uses and defs, and that all
instructions have a SlotIndex.

Stuff we don't check yet:

- Is the LiveInterval minimal?
- Do all defs correspond to instructions or phis?
- Do all defs dominate all their live ranges?
- Are all live ranges continually reachable from their def?

llvm-svn: 110386

be killed before being redefined.

These checks are usually disabled, and usually fail when enabled. We de facto
allow live registers to be redefined without a kill, the corresponding
assertions in RegScavenger were removed long ago.

llvm-svn: 110362

we sometimes compare singular iterators, reported by ENABLE_EXPENSIVE_CHECKS.
This fixes PR7825.

llvm-svn: 110355

because it could create such things. This fixes a MingW buildbot test failure.

llvm-svn: 110279

This helps avoid silly code:

    %R0<def = LOAD <fi#5>
    STORE <fi#5>, %R0<kill>

llvm-svn: 110266

We are now at a point where we can split around simple single-entry, single-exit
loops, although still with some bugs.

llvm-svn: 110257

llvm-svn: 110255

llvm-svn: 110248

llvm-svn: 110244

be triggered by valid, if dubious, IR.

llvm-svn: 110240

While spilling live registers at the end of block check whether they are used by DBG_VALUE machine instructions or not. If a spilled register is used by DBG_VALUE machine instruction then insert a new DBG_VALUE machine instruction to encode variable's new location on stack.

llvm-svn: 110235

llvm-svn: 110234