Generalize isPSHUFDMask and add a unary SHUFPD pattern so that SHUFPD's
memory operand alignment can be tested as well, with a fix to avoid
breaking MMX's use of isPSHUFDMask.

llvm-svn: 40756

llvm-svn: 40754

llvm-svn: 40751

llvm-svn: 40750

llvm-svn: 40749

llvm-svn: 40748

llvm-svn: 40746

llvm-svn: 40745

llvm-svn: 40743

casts in the input.

llvm-svn: 40741

llvm-svn: 40740

llvm-svn: 40739

gvn, gvnpre, dse, and predsimplify.  To see these, use:

  make check-line-length

llvm-svn: 40738

exit edge to preserve LCSSA.

Fix dominance frontier update during loop unswitch. This fixes PR 1589, again

llvm-svn: 40737

X86InstrInfo::isReallyTriviallyReMaterializable knows how to handle
with the isReMaterializable flag so that it is given a chance to handle
them. Without hoisting constant-pool loads from loops this isn't very
visible, though it does keep CodeGen/X86/constant-pool-remat-0.ll from
making a copy of the constant pool on the stack.

llvm-svn: 40736

operations of casts.  This implements InstCombine/zext-fold.ll

llvm-svn: 40726

llvm-svn: 40725

Add extend and extOrTrunc methods that do sign or zero extension depending on whether the integer is signed or not

llvm-svn: 40724

llvm-svn: 40723

llvm-svn: 40722

llvm-svn: 40721

llvm-svn: 40720

This fixes test/Feature/llvm2cpp.ll

llvm-svn: 40714

llvm-svn: 40712

llvm-svn: 40711

simply specify them as results and let scheduledag handle them. That
is, instead of
SDOperand Flag = DAG.getTargetNode(Opc, MVT::i32, MVT::Flag, ...)
SDOperand Result = DAG.getCopyFromReg(Chain, X86::EAX, MVT::i32, Flag)

Just write:
SDOperand Result = DAG.getTargetNode(Opc, MVT::i32, MVT::i32, ...)

And let scheduledag emit the move from X86::EAX to a virtual register.

llvm-svn: 40710

llvm-svn: 40709

llvm-svn: 40703

llvm-svn: 40702

llvm-svn: 40701

llvm-svn: 40698

llvm-svn: 40697

failure to assemble).

llvm-svn: 40696

exit edge to preserve LCSSA.

Fix dominance frontier update during loop unswitch. This fixes PR 1589.

llvm-svn: 40695

llvm-svn: 40692

llvm-svn: 40691

llvm-svn: 40690

llvm-svn: 40689

llvm-svn: 40688

llvm-svn: 40687