llvm-svn: 115605

bswap32 doesn't read eflags.

llvm-svn: 115604

pseudo instructions.

Move POPCNT to InstrSSE since they are SSE4 instructions.

llvm-svn: 115603

with the 32-bit stuff.

llvm-svn: 115602

llvm-svn: 115601

llvm-svn: 115600

llvm-svn: 115599

llvm-svn: 115598

llvm-svn: 115597

control flow stuff out to X86InstrControl.td.  Move
some compiler pseudo instructions and Pat<> patterns
out to X86InstrCompiler.td

llvm-svn: 115596

llvm-svn: 115591

else in X86), and add support for pavgusb.  This is apparently the
only instruction (other than movsx) that is preventing ffmpeg from building
with clang.

If someone else is interested in banging out the rest of the 3DNow! 
instructions, it should be quite easy now.

llvm-svn: 115466

llvm-svn: 115429

reflection, this isn't going to achieve the purpose I intended it for.  Back to the drawing board!

llvm-svn: 114710

llvm-svn: 114703

x86-32: 32-bit calls were named "call" not "calll".  64-bit calls were correctly
named "callq", so this only impacted x86-32.

This fixes rdar://8456370 - llvm-mc rejects 'calll'

This also exposes that mingw/64 is generating a 32-bit call instead of a 64-bit call,
I will file a bugzilla.

llvm-svn: 114534

llvm-svn: 114529

llvm-svn: 114515

by having X86DAGToDAGISel::SelectAddr get passed in the parent node
of the operand match (the load/store/atomic op) and having it get
the address space from that, instead of having special FS/GS addr
mode operations that require duplicating the entire instruction set
to support.

This makes FS and GS relative accesses *far* more predictable and
work much better.  It also simplifies the X86 backend a bit, more
to come.

There is still a pending issue with nodes like ISD::PREFETCH and
X86ISD::FLD, which really should be MemSDNode's but aren't.

llvm-svn: 114491

llvm-svn: 114468

What a weird instruction.

llvm-svn: 114190

add sldt GR32, which isn't documented in the intel manual
but which gas accepts.  Part of rdar://8418316

llvm-svn: 113938

llvm-svn: 113422

llvm-svn: 113350

fixing rdar://8403974

llvm-svn: 113349

rdar://8061602

llvm-svn: 113343

llvm-svn: 113259

allowing unsigned 8-bit operands.  This fixes rdar://8208481

llvm-svn: 113182

llvm-svn: 113158

llvm-svn: 112921

Mark _alloca call as clobberring EFLAGS, otherwise some DCE might remove
other flags-clobberring stuff (e.g. cmp instructions) occuring after
_alloca call.

llvm-svn: 112034

x86 int and int3 instructions.  Patch by Peter Housel!

llvm-svn: 111831

call and jumps.

llvm-svn: 111496

encoding is correct for the built-in assembler.

Based on a patch from Chris.

llvm-svn: 111083

llvm-svn: 110618

instructions.

llvm-svn: 110360

uses.

llvm-svn: 110274

llvm-svn: 109877

we are using AVX and no AVX version of the desired intruction is present,
this is better for incremental dev (without fallbacks it's easier to spot
what's missing). Not sure this is the best hack thought (we can also disable
all HasSSE* predicates by dinamically marking them 'false' if AVX is present)

llvm-svn: 109434

llvm-svn: 109206