llvm-svn: 111260

printing "lsl #0".  This fixes the remaining parts of pr7792.  Make
corresponding changes for encoding/decoding these instructions.

llvm-svn: 111251

llvm-svn: 111241

llvm-svn: 111226

we're adding predicates and optional defs to the MachineInstrs.

llvm-svn: 111222

llvm-svn: 111219

llvm-svn: 111208

that the high halfword is zero.  The shift need not be exactly 16 bits.

llvm-svn: 111196

llvm-svn: 111185

llvm-svn: 111182

llvm-svn: 111173

instructions besides saturate instructions.  No functional changes.

llvm-svn: 111168

clang says is unused.

llvm-svn: 111167

llvm-svn: 111155

llvm-svn: 111154

llvm-svn: 111102

encoding is correct for the built-in assembler.

Based on a patch from Chris.

llvm-svn: 111083

llvm-svn: 111082

llvm-svn: 111073

llvm-svn: 111068

This fixes another part of PR7792.

llvm-svn: 111057

llvm-svn: 111050

instruction opcode.  This fixes part of PR7792.

llvm-svn: 111047

llvm-svn: 111041

same lines as the change I made for ARM saturate instructions.

llvm-svn: 111029

misanalysis and is undesirable.

llvm-svn: 111028

llvm-svn: 111022

llvm-svn: 111021

llvm-svn: 111001

llvm-svn: 111000

llvm-svn: 110954

the memory barrier variants (other than 'SY' full system domain read and write)
are treated as one instruction with option operand.

llvm-svn: 110951

Make sure ARM constant island pass does not break up an IT block. If the split point is in the middle of an IT block, it should move it up to just above the IT instruction. rdar://8302637

llvm-svn: 110947

- Teach SSEDomainFix to switch between different levels of AVX instructions. Here we guess that AVX will have domain issues, so just implement them for consistency  and in the future we remove if it's unnecessary.
- Make foldMemoryOperandImpl aware of 256-bit zero vectors folding and support the 128-bit counterparts of AVX too.
- Make sure MOV[AU]PS instructions are only selected when SSE1 is enabled, and duplicate the patterns to match AVX.
- Add a testcase for a simple 128-bit zero vector creation.

llvm-svn: 110946

llvm-svn: 110937

llvm-svn: 110898

term goal here is to be able to match enough of vector_shuffle and build_vector
so all avx intrinsics which aren't mapped to their own built-ins but to
shufflevector calls can be codegen'd. This is the first (baby) step, support
building zeroed vectors.

llvm-svn: 110897

entry for ARM STRBT is actually a super-instruction for A8.6.199 STRBT A1 & A2.
Recover by looking for ARM:USAT encoding pattern before delegating to the auto-
gened decoder.

Added a "usat" test case to arm-tests.txt.

llvm-svn: 110894

because it could have an ambiguous suffix.

llvm-svn: 110890

instructions onto the target specific parser, which can do a better job.

llvm-svn: 110889