the register.  While we're at it, make sure it's in the right one.

llvm-svn: 105645

llvm-svn: 105634

llvm-svn: 105620

DeltaAlgorithm: Tweak split to split by first/second half instead of even/odd, since adjacent changes are more likely to be related.

llvm-svn: 105613

ADT: Add DAGDeltaAlgorithm, which is a DAG minimization algorithm built on top of the standard 'delta debugging' algorithm.
 - This can give substantial speedups in the delta process for inputs we can construct dependency information for.

llvm-svn: 105612

realloc implementation can try to expand the allocated memory block in-place,
avoiding the copy.

llvm-svn: 105605

Discussed here:
http://lists.cs.uiuc.edu/pipermail/llvmdev/2010-June/032107.html

llvm-svn: 105601

llvm-svn: 105591

- change isShuffleMaskLegal to show that all shuffles with 32-bit and 64-bit
  elements are legal
- the Neon shuffle instructions do not support 64-bit elements, but we were
  not checking for that before lowering shuffles to use them
- remove some 64-bit element vduplane patterns that are no longer needed

llvm-svn: 105586

that it is an immediate before checking that the instruction is an
EXTRACT_SUBREG.

llvm-svn: 105585

llvm-svn: 105561

rdar://7797940

llvm-svn: 105557

llvm-svn: 105554

llvm-svn: 105551

determinstic. Instead, give SCEV objects an arbitrary sequence
number.

llvm-svn: 105548

that the operands are sorted.

llvm-svn: 105546

the operands.

llvm-svn: 105545

llvm-svn: 105544

llvm-svn: 105542

llvm-svn: 105541

scrounging through SCEVUnknown contents and SCEVNAryExpr operands;
instead just do a simple deterministic comparison of the precomputed
hash data.

Also, since this is more precise, it eliminates the need for the slow
N^2 duplicate detection code.

llvm-svn: 105540

encapsulation to force the users of these classes to know about the internal
data structure of the Operands structure. It also can lead to errors, like in
the MSIL writer.

llvm-svn: 105539

Partial specialization was not checking the callsite to make sure it was using the same constants as the specialization, leading to calls to the wrong specialization.  Patch by Takumi Nakamura\!

llvm-svn: 105528

llvm-svn: 105527

In file included from X86InstrInfo.cpp:16:
X86GenInstrInfo.inc:2789: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2790: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2792: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2793: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2808: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2809: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2816: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2817: error: integer constant is too large for 'long' type

llvm-svn: 105524

yet, only assembly encoding support.

llvm-svn: 105521

unless using -arm-tail-calls.

llvm-svn: 105515

llvm-svn: 105514

llvm-svn: 105511

there could be multiple subexpressions within a single expansion which
require insert point adjustment. This fixes PR7306.

llvm-svn: 105510

I don't think this ever resulted in problems on x86, but it
would on ARM.

llvm-svn: 105509

llvm-svn: 105502

register pressure.

llvm-svn: 105501

llvm-svn: 105498

llvm-svn: 105492

Copy location info for current function argument from dbg.declare if respective store instruction does not have any location info.

llvm-svn: 105490

llvm-svn: 105481

llvm-svn: 105480

register allocation.

Process all of the clobber lists at the end of the function, marking the
registers as used in MachineRegisterInfo.

This is necessary in case the calls clobber callee-saved registers (sic).

llvm-svn: 105473

8060143, although this doesn't fix the real problem with tail call.

llvm-svn: 105472