During post RA scheduling, do not try to chase reg defs. to preserve DBG_VALUEs. This approach has several downsides, for example, it does not work when dbg value is a constant integer, it does not work if reg is defined more than once, it places end of debug value range markers in the wrong place. It even causes misleading incorrect debug info when duplicate DBG_VALUE instructions point to same reg def. 

Instead, use simpler approach and let DBG_VALUE follow its predecessor instruction. After live debug value analysis pass, all DBG_VALUE instruction are placed at the right place. Thanks Jakob for the hint!

llvm-svn: 132483

llvm-svn: 132482

llvm-svn: 132479

llvm-svn: 132477

Testcase will come when we use it.

Part of rdar://9119939

llvm-svn: 132476

llvm-svn: 132472

This saves two virtual function calls and an Allocatable BitVector test,
making RAFast run 2% faster.

llvm-svn: 132471

Parsing a register name/number for .cfi directives can't assume that a
register name starts with a '%' token. Be more flexible and check for a
register number instead. Still unlikely to be perfect, but it allows us
to parse both plain identifiers as register names and integers as register
numbers, which is what we're wanting to support at this point.

llvm-svn: 132466

rdar://problem/6373334

llvm-svn: 132458

Found by valgrind.

llvm-svn: 132457

llvm-svn: 132456

No functional change.

llvm-svn: 132455

llvm-svn: 132454

llvm-svn: 132451

register classes.

It provides information for each register class that cannot be
determined statically, like:

- The number of allocatable registers in a class after filtering out the
  reserved and invalid registers.

- The preferred allocation order with registers that overlap callee-saved
  registers last.

- The last callee-saved register that overlaps a given physical register.

This information usually doesn't change between functions, so it is
reused for compiling multiple functions when possible.  The many
possible combinations of reserved and callee saves registers makes it
unfeasible to compute this information statically in TableGen.

Use RegisterClassInfo to count available registers in various heuristics
in SimpleRegisterCoalescing, making the pass run 4% faster.

llvm-svn: 132450

llvm-svn: 132448

llvm-svn: 132445

llvm-svn: 132444

When marking a block as being unanalyzable, use "Clobber" on the terminator instead of the first instruction in the block.  This is a bit of a hack; "Clobber" isn't really the right marking in the first place.  memdep doesn't really have any way of properly expressing "unanalyzable" at the moment.  Using it on the terminator is much less ambiguous than using it on an arbitrary instruction, though.

In the given testcase, the "Clobber" was pointing to a load, and GVN was incorrectly assuming that meant that the "Clobber" load overlapped the load being analyzed (when they are actually unrelated).

The included testcase tests both this commit and r132434.

Part two of rdar://9429882.  (r132434 was mislabeled.)

llvm-svn: 132442

llvm-svn: 132437

In MemoryDependenceAnalysis::getNonLocalPointerDepFromBB, if a given block is is deemed unanalyzable (and we execute one of the "goto PredTranslationFailure" statements), make sure we don't put information about the predecessors of that block into the returned data structures; this can lead to, among other things, extraneous results (which will confuse passes using memdep).  Fixes an assert in GVN compiling ruby. Part of rdar://problem/9521954 .

Testcase coming up soon.

llvm-svn: 132434

llvm-svn: 132433

llvm-svn: 132427

llvm-svn: 132424

types if the vector type is legal.

Fixes rdar://9306086

llvm-svn: 132420

llvm-svn: 132419

the TargetLowering enum.

llvm-svn: 132418

llvm-svn: 132416

This commit caused regressions in i386 flops-[568], matrix, salsa20,
256.bzip2, and enc-md5.

llvm-svn: 132413

rdar://problem/5660695

llvm-svn: 132411

llvm-svn: 132409

llvm-svn: 132408

Fixes valgrind errors in the CellSPU backend.

llvm-svn: 132405

floating-point comparison, generate a mask of 0s or 1s, and generally
DTRT with NaNs.  Only profitable when the user wants a materialized 0
or 1 at runtime.  rdar://problem/5993888

llvm-svn: 132404

llvm-svn: 132402

valid for x87, re-target to x87.  rdar://problem/5993888

llvm-svn: 132401

llvm-svn: 132399

Add TargetRegisterInfo::hasSubClassEq and use it to check for compatible
register classes instead of trying to list all register classes in
X86's getLoadStoreRegOpcode.

llvm-svn: 132398

llvm-svn: 132396

llvm-svn: 132395