movlps cannot be used (e.g. when load from m64 has multiple uses).

llvm-svn: 28089

llvm-svn: 27968

result). Otherwise tblgen will pick the default (v16i8 for 128-bit vector).

llvm-svn: 27965

a temporary workaround for the 2-wide vector_shuffle problem (i.e. its mask
would have type v2i32 which is not legal).

llvm-svn: 27964

llvm-svn: 27960

scalar value.

e.g.
        _mm_set_epi32(0, a, 0, 0);
==>
	movd 4(%esp), %xmm0
	pshufd $69, %xmm0, %xmm0

        _mm_set_epi8(0, 0, 0, 0, 0, a, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
==>
	movzbw 4(%esp), %ax
	movzwl %ax, %eax
	pxor %xmm0, %xmm0
	pinsrw $5, %eax, %xmm0

llvm-svn: 27923

llvm-svn: 27844

- Added more movhlps and movlhps patterns.

llvm-svn: 27842

llvm-svn: 27836

- Increase cost (complexity) of patterns which match mov{h|l}ps ops. These
  are preferred over shufps in most cases.

llvm-svn: 27835

- PINSRWrmi encoding bug.

llvm-svn: 27818

llvm-svn: 27816

llvm-svn: 27814

llvm-svn: 27813

llvm-svn: 27807

llvm-svn: 27782

llvm-svn: 27773

llvm-svn: 27762

llvm-svn: 27734

llvm-svn: 27733

llvm-svn: 27722

llvm-svn: 27721

llvm-svn: 27720

llvm-svn: 27719

llvm-svn: 27715

llvm-svn: 27711

llvm-svn: 27699

llvm-svn: 27685

llvm-svn: 27684

llvm-svn: 27668

llvm-svn: 27647

llvm-svn: 27645

llvm-svn: 27639

llvm-svn: 27638

llvm-svn: 27637

Clean up and fix various logical ops issues.

llvm-svn: 27633

llvm-svn: 27612

llvm-svn: 27603

__builtin_ia32_loadlv4si, __builtin_ia32_loaddqu, __builtin_ia32_storedqu.

llvm-svn: 27599

later.

llvm-svn: 27591