register names in the standalone assembler llvm-mc.

Registers such as $A1 can represent either a 32 or
64 bit register based on the instruction using it.
In addition, based on the abi, $T0 can represent different
32 bit registers.


The problem is resolved by the Mips specific AsmParser 
td definitions changing to work together. Many cases of
RegisterClass parameters are now RegisterOperand.


Contributer: Vladimir Medic
llvm-svn: 172284

parameter.

llvm-svn: 170661

No functionality change.

llvm-svn: 170084

No functionality change.

llvm-svn: 170077

No functionality change.

llvm-svn: 170076

No functionality change.

llvm-svn: 170075

No functionality change.

llvm-svn: 170073

No functionality change.

llvm-svn: 170072

No functionality change.

llvm-svn: 170071

No functionality change.

llvm-svn: 170069

and separate encoding information from the rest.

llvm-svn: 170066

MipsInstrFPU.td.
 

llvm-svn: 170061

 

llvm-svn: 170060

 

llvm-svn: 170057

FFR2P_M.
 

llvm-svn: 170055

FFR1_W_M and FFR1P_M. The new instruction definitions have one-to-one
correspondence with the instructions in the ISA manual.
 

llvm-svn: 170053

llvm-svn: 169579

support and use it in place of HasMips32r2Or64.

llvm-svn: 168089

instructions.

llvm-svn: 167348

use load/store fragments defined in TargetSelectionDAG.td in place of them.
Unaligned loads/stores are either expanded or lowered to target-specific nodes,
so instruction selection should see only aligned load/store nodes.

No changes in functionality.

llvm-svn: 163960

Patch by Vladimir Medic.

llvm-svn: 162124

or not it is in mips16 mode. Define MipsPseudo (mode-independant pseudo) and
PseudoSE (mips32/64 pseudo) classes.

llvm-svn: 161071

single-precision load and store.

Also avoid selecting LUXC1 and SUXC1 instructions during isel. It is incorrect
to map unaligned floating point load/store nodes to these instructions.

llvm-svn: 161063

being used by Mips16 or Micro Mips
2. clean up a few lines too long encountered

Patch by Reed Kotler.

llvm-svn: 158470

instruction encodings can be excluded during mips16 processing.

This revision fixes the issue raised by Jim Grosbach.

bool hasStandardEncoding() const { return !inMips16Mode(); }

When micromips is added it will be

bool StandardEncoding() const { return !inMips16Mode()&&  !inMicroMipsMode(); }

No additional testing is needed other than to assure that there is no regression
from this patch.

Patch by Reed Kotler.

llvm-svn: 157234

Patch by Vladimir Medic. 

llvm-svn: 154935

otherwise expand FNEG during legalization.

llvm-svn: 154546

Invalid operation is signaled if the operand of these instructions is NaN.

llvm-svn: 154545

llvm-svn: 153925

Patch by Vladimir Medic.

llvm-svn: 153924

and stores was added.

- SelectAddr should return false if Parent is an unaligned f32 load or store.
- Only aligned load and store nodes should be matched to select reg+imm
  floating point instructions.
- MIPS does not have support for f64 unaligned load or store instructions.

llvm-svn: 151843

llvm-svn: 151625

load and store instructions.

llvm-svn: 151611

llvm-svn: 151540

llvm-svn: 151538

add/sub instructions.

llvm-svn: 151415

llvm-svn: 150706

llvm-svn: 148869

llvm-svn: 144019

and add Mips64's version too.

llvm-svn: 144018