FIX PR7158. SimplifyVBinOp was asserting when it fails to constant fold (op (build_vector), (build_vector)). 

llvm-svn: 104004

Fix PR7175. Insert copies of a REG_SEQUENCE source if it is used by other REG_SEQUENCE instructions.

llvm-svn: 103994

- Change the logic DisableFramePointerElim() to check for the
  -disable-non-leaf-fp-elim before -disable-fp-elim.

llvm-svn: 103990

and cleanup comments as well.

llvm-svn: 103985

Fix PR7156. If the sources of a REG_SEQUENCE are all IMPLICIT_DEF's. Replace it with an IMPLICIT_DEF rather than deleting it or else it would be left without a def.

llvm-svn: 103984

This fixes the miscompilations of MultiSource/Applications/JM/l{en,de}cod.
Clang now successfully self hosts in a debug build with the fast register allocator.

llvm-svn: 103975

llvm-svn: 103974

llvm-svn: 103971

llvm-svn: 103961

While that approach works wonders for register pressure, it tends to break
everything.

This should unbreak the arm-linux builder and fix a number of miscompilations.

llvm-svn: 103946

llvm-svn: 103940

out aliases when allocating. Clean up allocVirtReg().

Use calcSpillCost() to allow more aggressive hinting. Now the hint is always
taken unless blocked by a reserved register. This leads to more coalescing,
lower register pressure, and less spilling.

llvm-svn: 103939

llvm-svn: 103936

This makes allocation independent on the ordering of use-def chains.

llvm-svn: 103935

llvm-svn: 103934

This is safe to do because the physreg has been marked UsedInInstr and the kill flag will be set on the last operand using the virtreg if there are more then one.

llvm-svn: 103933

llvm-svn: 103931

through the very long list of call-clobbered registers. We just assume all
registers are clobbered.

llvm-svn: 103930

llvm-svn: 103929

Debug code doesn't use callee saved registers anyway, and the code is simpler this way. Now spillVirtReg always kills, and the isKill parameter is not needed.

llvm-svn: 103927

llvm-svn: 103926

llvm-svn: 103925

Yes, if the redef is a copy, update the old val# with the copy. But make sure to clear the copy field if the redef is not a copy.

llvm-svn: 103922

The implementation in LegalizeIntegerTypes to handle this as 
sint64->float + appropriate power of 2 is subject to double rounding,
considered incorrect by numerics people.  Use this implementation only
when it is safe.  This leads to using library calls in some cases
that produced inline code before, but it's correct now.
(EVTToAPFloatSemantics belongs somewhere else, any suggestions?)

Add a correctly rounding (though not particularly fast) conversion
that uses X87 80-bit computations for x86-32.

7885399, 5901940.  This shows up in gcc.c-torture/execute/ieee/rbug.c
in the gcc testsuite on some platforms.

llvm-svn: 103883

llvm-svn: 103882

patch by Evzen Muller!

llvm-svn: 103876

a condition's grouping. Every other use of Allocatable.test(Hint) groups it the
same way as it is indented, so move the parentheses to agree with that
grouping.

llvm-svn: 103869

When working top-down in a basic block, substituting physregs for virtregs, the use-def chains are kept up to date. That means we can recognize a virtreg kill by the use-def chain becoming empty.

This makes the fast allocator independent of incoming kill flags.

llvm-svn: 103866

llvm-svn: 103850

instructions.

e.g.
%reg1026<def> = VLDMQ %reg1025<kill>, 260, pred:14, pred:%reg0
%reg1027<def> = EXTRACT_SUBREG %reg1026, 6
%reg1028<def> = EXTRACT_SUBREG %reg1026<kill>, 5
...
%reg1029<def> = REG_SEQUENCE %reg1028<kill>, 5, %reg1027<kill>, 6, %reg1028, 7, %reg1027, 8, %reg1028, 9, %reg1027, 10, %reg1030<kill>, 11, %reg1032<kill>, 12

After REG_SEQUENCE is eliminated, we are left with:

%reg1026<def> = VLDMQ %reg1025<kill>, 260, pred:14, pred:%reg0
%reg1029:6<def> = EXTRACT_SUBREG %reg1026, 6
%reg1029:5<def> = EXTRACT_SUBREG %reg1026<kill>, 5

The regular coalescer will not be able to coalesce reg1026 and reg1029 because it doesn't
know how to combine sub-register indices 5 and 6. Now 2-address pass will consult the
target whether sub-registers 5 and 6 of reg1026 can be combined to into a larger
sub-register (or combined to be reg1026 itself as is the case here). If it is possible, 
it will be able to replace references of reg1026 with reg1029 + the larger sub-register
index.

llvm-svn: 103835

setting kill flags.

llvm-svn: 103832

llvm-svn: 103831

llvm-svn: 103830

llvm-svn: 103828

llvm-svn: 103827

llvm-svn: 103823

llvm-svn: 103822

llvm-svn: 103821

llvm-svn: 103820

llvm-svn: 103807