branch).

llvm-svn: 172740

This patch fixes bug 14902 - http://llvm.org/bugs/show_bug.cgi?id=14902

llvm-svn: 172737

llvm-svn: 172736

[ObjCARC] Implemented operator<< for InstructionClass and changed a ``Visited'' Debug message to use it.

llvm-svn: 172735

Reverting back to the fallback instead of using popcnt; this instruction doesn't exist on all CPU architectures.  Fixes PR14982

llvm-svn: 172734

_Complex float and _Complex long double, by simply increasing the
number of floating point registers available for return values.

The test case verifies that the correct registers are loaded.

llvm-svn: 172733

ASan: add optional 'zero-based shadow' option to ASan passes. Always tell the values of shadow scale and offset to the runtime

llvm-svn: 172709

v8i8  -> v8i64, 
v8i8  -> v8i32, 
v4i8  -> v4i64, 
v4i16 -> v4i64 
for AVX and AVX2.

Bug 14865.

llvm-svn: 172708

Combine AVX and SSE forms of MOVSS and MOVSD into the same multiclasses so they get instantiated together.

llvm-svn: 172704

changing both the string of the dwo_name to be correct and the type of
the statement list.

Testcases all around.

llvm-svn: 172699

emitting the dwarf32 version of DW_FORM_sec_offset and correct
disassembler support.

llvm-svn: 172698

Let targets use it.

llvm-svn: 172688

Move the early if-conversion pass into this group.

ILP optimizations usually need to find the right balance between
register pressure and ILP using the MachineTraceMetrics analysis to
identify critical paths and estimate other costs. Such passes should run
together so they can share dominator tree and loop info analyses.

Besides if-conversion, future passes to run here here could include
expression height reduction and ARM's MLxExpansion pass.

llvm-svn: 172687

but I cannot reproduce the problem and have scrubed my sources and
even tested with llvm-lit -v --vg.

The Mips RDHWR (Read Hardware Register) instruction was not 
tested for assembler or dissassembler consumption. This patch
adds that functionality.

Contributer: Vladimir Medic
 
llvm-svn: 172685

llvm-svn: 172681

ambiguous term 'legal'.

Suggested by Andrew Booker. Thanks Andrew!

llvm-svn: 172680

Reported on IRC by _savage

llvm-svn: 172677

llvm-svn: 172670

llvm-svn: 172659

Moving the X86CostTable to a common place, so that other back-ends
can share the code. Also simplifying it a bit and commoning up
tables with one and two types on operations.

llvm-svn: 172658

llvm-svn: 172656

llvm-svn: 172655

llvm-svn: 172652

llvm-svn: 172651

llvm-svn: 172646

Patch by Jakub Staszak.

llvm-svn: 172645

llvm-svn: 172644

llvm-svn: 172642

llvm-svn: 172640

llvm-svn: 172638

return into the safe harbor of AsmParser's private areas.

llvm-svn: 172637

 - Instead of computing a bunch of buckets of different flag types, just do an
   incremental link resolving conflicts as they arise.

 - This also has the advantage of making the link result deterministic and not
   dependent on map iteration order.

llvm-svn: 172634

AT_producer.  Which includes clang's version information so we can tell
which version of the compiler was used.

This is the first of two steps to allow us to do that.  This is the llvm-mc
change to provide a method to set the AT_producer string.  The second step,
coming soon to a clang near you, will have the clang driver pass the value
of getClangFullVersion() via an flag when invoking the integrated assembler
on assembly source files.

rdar://12955296

llvm-svn: 172630

In r143502, we renamed getHostTriple() to getDefaultTargetTriple()
as part of work to allow the user to supply a different default
target triple at configure time.  This change also affected the JIT.
However, it is inappropriate to use the default target triple in the
JIT in most circumstances because this will not necessarily match
the current architecture used by the process, leading to illegal
instruction and other such errors at run time.

Introduce the getProcessTriple() function for use in the JIT and
its clients, and cause the JIT to use it.  On architectures with a
single bitness, the host and process triples are identical.  On other
architectures, the host triple represents the architecture of the
host CPU, while the process triple represents the architecture used
by the host CPU to interpret machine code within the current process.
For example, when executing 32-bit code on a 64-bit Linux machine,
the host triple may be 'x86_64-unknown-linux-gnu', while the process
triple may be 'i386-unknown-linux-gnu'.

This fixes JIT for the 32-on-64-bit (and vice versa) build on non-Apple
platforms.

Differential Revision: http://llvm-reviews.chandlerc.com/D254

llvm-svn: 172627

llvm-svn: 172622

llvm-svn: 172615

llvm-svn: 172614

llvm-svn: 172612

Should fix the arm buildbot (which only builds the arm target).

llvm-svn: 172611

ASan: wrap mapping scale and offset in a struct and make it a member of ASan passes. Add test for non-default mapping scale and offset. No functionality change

llvm-svn: 172610