isRegister, isImmediate, and isMachineBasicBlock, which are equivalent,
and more popular.

llvm-svn: 41958

llvm-svn: 41739

Use pool allocator for all the VNInfo's to improve memory access locality. This reduces coalescing time on siod Mac OS X PPC by 35%. Also remove the back ptr from VNInfo to LiveInterval and other tweaks.

llvm-svn: 41729

llvm-svn: 41598

Changes related modules so VNInfo's are not copied. This decrease
copy coalescing time by 45% and overall compilation time by 10% on siod.

llvm-svn: 41579

Fix some kill info update bugs; add hidden option -disable-rematerialization to turn off remat for debugging.

llvm-svn: 41118

Re-implement trivial rematerialization. This allows def MIs whose live intervals that are coalesced to be rematerialized.

llvm-svn: 41060

llvm-svn: 41016

llvm-svn: 40925

- Fix some minor bugs related to special markers on val# def. ~0U means
  undefined, ~1U means dead val#.

llvm-svn: 40916

kill instruction #, and source register number (iff the value# is defined by a
copy).
- Now def instruction # is set for every value#, not just for copy defined ones.
- Update some outdated code related inactive live ranges.
- Kill info not yet set. That's next patch.

llvm-svn: 40913

llvm-svn: 37764

llvm-svn: 37743

with a general target hook to identify rematerializable instructions. Some
instructions are only rematerializable with specific operands, such as loads
from constant pools, while others are always rematerializable. This hook
allows both to be identified as being rematerializable with the same
mechanism.

llvm-svn: 37644

implementation for x86.

llvm-svn: 37576

simultaneously.  Move that pass to SimpleRegisterCoalescing.

This makes it easier to implement alternative register allocation and
coalescing strategies while maintaining reuse of the existing live
interval analysis.

llvm-svn: 37520

llvm-svn: 37052

v1 =
r2 = move v1
   = op r2<kill>
...
r2 = move v1
   = op r2<kill>

Clear the first r2 kill if v1 and r2 are joined.

llvm-svn: 37050

llvm-svn: 36662

Due to darwin gcc bug, one version of darwin linker coalesces
static const int, which defauts PassID based pass identification.

llvm-svn: 36652

llvm-svn: 36648

llvm-svn: 36632

llvm-svn: 36483

- A register def / use now implicitly affects sub-register liveness but does
not affect liveness information of super-registers.
- Def of a larger register (if followed by a use later) is treated as
read/mod/write of a smaller register.

llvm-svn: 36434

llvm-svn: 36250

llvm-svn: 36240

long live interval that has low usage density.
1. Change order of coalescing to join physical registers with virtual
   registers first before virtual register intervals become too long.
2. Check size and usage density to determine if it's worthwhile to join.
3. If joining is aborted, assign virtual register live interval allocation
   preference field to the physical register.
4. Register allocator should try to allocate to the preferred register
   first (if available) to create identify moves that can be eliminated.

llvm-svn: 36218

llvm-svn: 35660

Trivially re-materializable instructions have spill weights that are half of what it would be otherwise.

llvm-svn: 35658

llvm-svn: 35600

of dead def live interval at 1 to avoid multiple def's targeting the same
register. The previous patch missed a case where the source operand is live-in.
In that case, remove the whole interval.

llvm-svn: 35512

llvm-svn: 35419

not violate that.

llvm-svn: 35396

llvm-svn: 35365

where the destination is dead.

llvm-svn: 35252

llvm-svn: 35208

llvm-svn: 35165

llvm-svn: 35153

- Use distance to closest use to determine whether to abort coalescing.

llvm-svn: 35141

to be really bad. Once they are joined they are not broken apart. Also, physical
intervals cannot be spilled!

Added a heuristic as a workaround for this. Be careful coalescing with a
physical register if the virtual register uses are "far". Check if there are
uses in the same loop as the source (copy instruction). Check if it is in the
loop preheader, etc.

llvm-svn: 35134