being used by Mips16 or Micro Mips
2. clean up a few lines too long encountered

Patch by Reed Kotler.

llvm-svn: 158470

instruction encodings can be excluded during mips16 processing.

This revision fixes the issue raised by Jim Grosbach.

bool hasStandardEncoding() const { return !inMips16Mode(); }

When micromips is added it will be

bool StandardEncoding() const { return !inMips16Mode()&&  !inMicroMipsMode(); }

No additional testing is needed other than to assure that there is no regression
from this patch.

Patch by Reed Kotler.

llvm-svn: 157234

Patch by Vladimir Medic. 

llvm-svn: 154935

otherwise expand FNEG during legalization.

llvm-svn: 154546

Invalid operation is signaled if the operand of these instructions is NaN.

llvm-svn: 154545

llvm-svn: 153925

Patch by Vladimir Medic.

llvm-svn: 153924

and stores was added.

- SelectAddr should return false if Parent is an unaligned f32 load or store.
- Only aligned load and store nodes should be matched to select reg+imm
  floating point instructions.
- MIPS does not have support for f64 unaligned load or store instructions.

llvm-svn: 151843

llvm-svn: 151625

load and store instructions.

llvm-svn: 151611

llvm-svn: 151540

llvm-svn: 151538

add/sub instructions.

llvm-svn: 151415

llvm-svn: 150706

llvm-svn: 148869

llvm-svn: 144019

and add Mips64's version too.

llvm-svn: 144018

floating pointer registers.

llvm-svn: 144016

-Fix binary codes and rename operands in .td files so that automatically
generated function MipsCodeEmitter::getBinaryCodeForInstr gives correct
encoding for instructions.
-Define new class FMem for instructions that access memory.
-Define new class FFRGPR for instructions that move data between GPR and
FPU general and control registers.
-Define custom encoder methods for memory operands, and also for size
operands of ext and ins instructions.
-Only static relocation model is currently implemented.

Patch by Sasa Stankovic

llvm-svn: 142378

llvm-svn: 142220

that have 64-bit pointers or access the 32 x 64-bit floating pointer register
file. Update functions in MipsInstrInfo.cpp too.

llvm-svn: 141623

llvm-svn: 141476

llvm-svn: 141475

llvm-svn: 141474

conversion instructions. 

llvm-svn: 141473

It broke the unit tests.  Please reapply with tests fixed.

llvm-svn: 140735

multiclasses.

llvm-svn: 140731

llvm-svn: 140705

llvm-svn: 140704

llvm-svn: 140661

of the instruction definitions using Pat<>.

llvm-svn: 140644

complain it cannot infer types in patterns. Fix a mistake in definition of 
SDT_MipsExtractElementF64.

llvm-svn: 140354

llvm-svn: 139405

Mips1 does not support double precision loads or stores, therefore two single
precision loads or stores must be used in place of these instructions. This 
patch treats double precision loads and stores as if they are legal
instructions until MCInstLowering, instead of generating the single precision
instructions during instruction selection or Prolog/Epilog code insertion.

Without the changes made in this patch, llc produces code that has the same 
problem described in r137484 or bails out when
MipsInstrInfo::storeRegToStackSlot or loadRegFromStackSlot is called before
register allocation.

llvm-svn: 137711

llvm-svn: 132718

llvm-svn: 131927

llvm-svn: 131233

Patch by Liu <proljc@gmail.com>!

llvm-svn: 131086

llvm-svn: 129612

Fix lines that have incorrect indentation or exceed 80 columns. There is no change in functionality.

llvm-svn: 129606