Fix some potential issues in the pseudo instruction expansion phase: copy implicit operands and memoperands. Also, expand instructions even if their defs are "dead" since they may have implicit kill operands.

llvm-svn: 103667

llvm-svn: 103642

llvm-svn: 103576

v1024 = REG_SEQUENCE ...
v1025 = EXTRACT_SUBREG v1024, 5
v1026 = EXTRACR_SUBREG v1024, 6
      = VSTxx <addr>, v1025, v1026

The REG_SEQUENCE ensures the sources that feed into the VST instruction
are getting the right register allocation so they form a large super-
register. The extract_subreg will be coalesced away all would just work:
v1024 = REG_SEQUENCE ...
      = VSTxx <addr>, v1024:5, v1024:6

The problem is if the coalescer isn't run, the extract_subreg instructions
would stick around and there is no assurance v1025 and v1026 will get the
right registers.

As a short term workaround, teach the NEON pre-allocation pass to transfer
the sub-register indices over. An alternative would be do it 2addr pass
when reg_sequence's are eliminated. But that *seems* wrong and require
updating liveness information.

Another alternative is to do this in the scheduler when the instructions are
created. But that would mean somehow the scheduler this has to be done for
correctness reason. That's yucky as well. So for now, we are leaving this
in the target specific pass.

llvm-svn: 103540

llvm-svn: 103513

to LLVM_LIBRARY_VISIBILITY and introduce LLVM_GLOBAL_VISIBILITY, which is
the opposite, for future use by dragonegg.

llvm-svn: 103495

Move EmitTargetCodeForMemcpy, EmitTargetCodeForMemset, and
EmitTargetCodeForMemmove out of TargetLowering and into
SelectionDAGInfo to exercise this.

llvm-svn: 103481

was unused. TargetMachine::getSubtarget() is used instead.

llvm-svn: 103474

llvm-svn: 103459

llvm-svn: 103453

llvm-svn: 103437

llvm-svn: 103411

whether the extract instructions are available.

rdar://7956878

llvm-svn: 103277

Use VLD2q32 / VST2q32 to reload / spill QQ (pair of Q) registers when stack slot is sufficiently aligned. Use VLDMD / VSTMD otherwise.

llvm-svn: 103235

Use VSTMD / VLDMD for spills and reloads of Q registers instead of VSTMQ / VLDQ. The later are aliases which ought to be eliminated but we can't because they are used for storing and loading v2f64 values.

llvm-svn: 103234

Remove VLD1q and VST1q for reloading and spilling Q registers. Just use VLD1q64 / VST1q64 and reference sub-registers.

llvm-svn: 103218

doesn't have to guess.

llvm-svn: 103194

llvm-svn: 103193

(replacing the previous patch for the same issue).

llvm-svn: 103183

llvm-svn: 103181

llvm-svn: 103179

Re-apply 103156 and 103157. 103156 didn't break anything. 10315 exposed a coalescer bug that's fixed by 103170.

llvm-svn: 103172

llvm-svn: 103163

   Reverse-merging r103156 into '.':
U    lib/Target/ARM/ARMInstrNEON.td
U    lib/Target/ARM/ARMRegisterInfo.h
U    lib/Target/ARM/ARMBaseRegisterInfo.cpp
U    lib/Target/ARM/ARMBaseInstrInfo.cpp
U    lib/Target/ARM/ARMRegisterInfo.td

llvm-svn: 103159

llvm-svn: 103157

Adding pseudo 256-bit registers QQ0 . . . QQ7 to represent pairs of Q registers. These will be used to model VLD2 / VST2 instructions in order to get substantially better codegen for them.

llvm-svn: 103156

llvm-svn: 103155

llvm-svn: 103154

instructions to subtarget features and update tests to reflect.
PR5717.

llvm-svn: 103136

Do not pre-allocate references of D registers pairs if they are extracted from the same Q register and are in the right order.

llvm-svn: 103124

Jordy <snhjordy@gmail.com>.

Followup patches will add some tests and adjust to use Subtarget features
for the instructions.

llvm-svn: 103119

llvm-svn: 103104

With -neon-reg-sequence, models forming a Q register from a pair of consecutive D registers as a REG_SEQUENCE.

llvm-svn: 103047

llvm-svn: 103041

eliminateFrameIndex(), leading to llvm_unreachable() assertion failure.

llvm-svn: 102980

changes before doing phi lowering for switches.

llvm-svn: 102809

llvm-svn: 102577

Add sizes non-floating point versions for the eh sjlj intrinsic expansions.

rdar://7895451

llvm-svn: 102526

Radar 7896289

llvm-svn: 102396

llvm-svn: 102373