Part of rdar://9643582

llvm-svn: 134095

llvm-svn: 134094

The tSpill and tRestore instructions are just copies of the tSTRspi and
tLDRspi instructions, respectively. Just use those directly instead.

llvm-svn: 134092

llvm-svn: 134089

getRegForInlineAsmConstraint.

Part of rdar://9643582

llvm-svn: 134088

llvm-svn: 134087

creating a few specific register classes.

Part of rdar://9643582

llvm-svn: 134086

for the port.

Part of rdar://9643582

llvm-svn: 134085

Part of rdar://9643582

llvm-svn: 134084

Part of rdar://9643582

llvm-svn: 134083

getRegForInlineAsmConstraint.

Part of rdar://9643582

llvm-svn: 134080

via vectors.

Part of rdar://9643582

llvm-svn: 134079

llvm-svn: 134055

llvm-svn: 134049

llvm-svn: 134030

llvm-svn: 134027

llvm-svn: 134026

llvm-svn: 134024

sink them into MC layer.
- Added MCInstrInfo, which captures the tablegen generated static data. Chang
TargetInstrInfo so it's based off MCInstrInfo.

llvm-svn: 134021

Drop the FpMov instructions, use plain COPY instead.

Drop the FpSET/GET instruction for accessing fixed stack positions.
Instead use normal COPY to/from ST registers around inline assembly, and
provide a single new FpPOP_RETVAL instruction that can access the return
value(s) from a call. This is still necessary since you cannot tell from
the CALL instruction alone if it returns anything on the FP stack. Teach
fast isel to use this.

This provides a much more robust way of handling fixed stack registers -
we can tolerate arbitrary FP stack instructions inserted around calls
and inline assembly. Live range splitting could sometimes break x87 code
by inserting spill code in unfortunate places.

As a bonus we handle floating point inline assembly correctly now.

llvm-svn: 134018

llvm-svn: 134014

llvm-svn: 134005

llvm-svn: 133989

When the destination operand is the same as the first source register
operand for arithmetic instructions, the destination operand may be omitted.

For example, the following two instructions are equivalent:
and r1, #ff
and r1, r1, #ff

rdar://9672867

llvm-svn: 133973

Correctly parse the forms of the Thumb mov-immediate instruction:
  1. 8-bit immediate 0-255.
  2. 12-bit shifted-immediate.

The 16-bit immediate "movw" form is also legal with just a "mov" mnemonic,
but is not yet supported. More parser logic necessary there due to fixups.

llvm-svn: 133966

Thumb2 MOV mnemonic can accept both cc_out and predication. We don't (yet)
encode the instruction properly, but this gets the parsing part.

llvm-svn: 133945

llvm-svn: 133944

llvm-svn: 133939

llvm-svn: 133938

llvm-svn: 133936

Add aliases for the vpush/vpop mnemonics to the VFP load/store multiple
writeback instructions w/ SP as the base pointer.

rdar://9683231

llvm-svn: 133932

When the destination operand is the same as the first source register
operand for arithmetic instructions, the destination operand may be omitted.

For example, the following two instructions are equivalent:
  sub r2, r2, #6
  sub r2, #6

rdar://9682597

llvm-svn: 133925

into XXXGenRegisterInfo.inc.

llvm-svn: 133922

This allows for more live scratch registers which is needed to handle
live ST registers before return and inline asm instructions.

llvm-svn: 133903

llvm-svn: 133874

The .b8 operations in PTX are far more limiting than I first thought. The mov operation isn't even supported, so there's no way of converting a .pred value into a .b8 without going via .b16, which is
not sensible. An improved implementation needs to use the fact that loads and stores automatically extend and truncate to implement support for EXTLOAD and TRUNCSTORE in order to correctly support
boolean values.

llvm-svn: 133873

<rdar://problem/9483883>

llvm-svn: 133858

llvm-svn: 133853

llvm-svn: 133847

llvm-svn: 133846