'' is not a recognized processor for this target (ignoring processor)

instead of:

 is not a recognized processor for this target (ignoring processor)

llvm-svn: 23256

are allowed to generate 64-bit-only PowerPC instructions for 32 bit hosts,
such as the PowerPC 970.

This speeds up 189.lucas from 81.99 to 32.64 seconds.

llvm-svn: 23250

llvm-svn: 23246

llvm-svn: 23245

generate the fun in-register fp<->long instructions.

llvm-svn: 23244

llvm-svn: 23241

llvm-svn: 23240

llvm-svn: 23239

llvm-svn: 23238

switch should never be exited, so its bottom is now unreachable.

llvm-svn: 23234

Define the PatFrag class which can be used to define subpatterns to match
things with.  Define 'not', and use it to define the patterns for andc,
nand, etc.

llvm-svn: 23233

llvm-svn: 23232

currently don't do anything.  This elides patterns for binary operators
that ping on the carry flag, since we don't model it yet.

This patch also removes PPC::SUB, because it is dead.

llvm-svn: 23230

llvm-svn: 23226

llvm-svn: 23222

llvm-svn: 23220

Remove the -enable-gpopt option which is subsumed by feature flags.

llvm-svn: 23218

llvm-svn: 23210

llvm-svn: 23209

llvm-svn: 23207

llvm-svn: 23202

the observation that it only has to handle i1 -> i64 and i64 -> i1.

llvm-svn: 23201

the results of calls to functions returning small values are properly
sign/zero extended.

llvm-svn: 23198

Align functions to 16-byte boundaries, to eliminate noise in performance measurements.  This improves the performance of 'treeadd' by about 20% with the dag
isel, restoring it to the pattern-isel level (which happens to get the alignment right).

llvm-svn: 23194

platforms.  This reduces executable size and makes shark realize the actual
bounds of functions instead of showing each MBB as a function :)

llvm-svn: 23193

1. Use SubtargetFeatures in llc/lli.

2. Propagate feature "string" to all targets.

3. Implement use of SubtargetFeatures in PowerPCTargetSubtarget.

llvm-svn: 23192

is to manage processor specific attributes from the command line.  See examples
of use in llc/lli and PowerPCTargetSubtarget.

llvm-svn: 23191

directly out of R1 (without using a CopyFromReg, which uses a chain), multiple
allocas were getting CSE'd together, producing bogus code.  For this:

int %foo(bool %X, int %A, int %B) {
        br bool %X, label %T, label %F
F:
        %G = alloca int
        %H = alloca int
        store int %A, int* %G
        store int %B, int* %H
        %R = load int* %G
        ret int %R
T:
        ret int 0
}

We were generating:

_foo:
        stwu r1, -16(r1)
        stw r31, 4(r1)
        or r31, r1, r1
        stw r1, 12(r31)
        cmpwi cr0, r3, 0
        bne cr0, .LBB_foo_2     ; T
.LBB_foo_1:     ; F
        li r2, 16
        subf r2, r2, r1   ;; One alloca
        or r1, r2, r2
        or r3, r1, r1
        or r1, r2, r2
        or r2, r1, r1
        stw r4, 0(r3)
        stw r5, 0(r2)
        lwz r3, 0(r3)
        lwz r1, 12(r31)
        lwz r31, 4(r31)
        lwz r1, 0(r1)
        blr
.LBB_foo_2:     ; T
        li r3, 0
        lwz r1, 12(r31)
        lwz r31, 4(r31)
        lwz r1, 0(r1)
        blr

Now we generate:

_foo:
        stwu r1, -16(r1)
        stw r31, 4(r1)
        or r31, r1, r1
        stw r1, 12(r31)
        cmpwi cr0, r3, 0
        bne cr0, .LBB_foo_2     ; T
.LBB_foo_1:     ; F
        or r2, r1, r1
        li r3, 16
        subf r2, r3, r2  ;; Alloca 1
        or r1, r2, r2
        or r2, r1, r1
        or r6, r1, r1
        subf r3, r3, r6  ;; Alloca 2
        or r1, r3, r3
        or r3, r1, r1
        stw r4, 0(r2)
        stw r5, 0(r3)
        lwz r3, 0(r2)
        lwz r1, 12(r31)
        lwz r31, 4(r31)
        lwz r1, 0(r1)
        blr
.LBB_foo_2:     ; T
        li r3, 0
        lwz r1, 12(r31)
        lwz r31, 4(r31)
        lwz r1, 0(r1)
        blr

This fixes Povray and SPASS with the dag isel, the last two failing cases.
Tommorow we will hopefully turn it on by default! :)

llvm-svn: 23190

could cause a miscompile.  Fixing this didn't fix the two programs that fail
though.  :(

This also changes the implementation to follow the pattern selector more
closely, causing us to select 0 to li instead of lis.

llvm-svn: 23189

and selecting early prevents folding immediates into the cmpw* instructions

llvm-svn: 23188

getting them out of the business of making stack slots.

llvm-svn: 23180

llvm-svn: 23179

llvm-svn: 23178

llvm-svn: 23177

the ops to dag optimization.

llvm-svn: 23176

llvm-svn: 23171

llvm-svn: 23170

llvm-svn: 23168

fixes crafty and probably others.

llvm-svn: 23167

ugly hacks

llvm-svn: 23162