Scalar SSE: a < b ? c : 0.0 -> cmpss, andps
Scalar SSE: float -> i16 needs to be promoted

llvm-svn: 22637

working, and Olden/power.

llvm-svn: 22441

XMM registers.  There are many known deficiencies and fixmes, which will be
addressed ASAP.  The major benefit of this work is that it will allow the
LLVM register allocator to allocate FP registers across basic blocks.

The x86 backend will still default to x87 style FP.  To enable this work,
you must pass -enable-sse-scalar-fp and either -sse2 or -sse3 to llc.

An example before and after would be for:
double foo(double *P) { double Sum = 0; int i; for (i = 0; i < 1000; ++i)
                        Sum += P[i]; return Sum; }

The inner loop looks like the following:
x87:
.LBB_foo_1:     # no_exit
        fldl (%esp)
        faddl (%eax,%ecx,8)
        fstpl (%esp)
        incl %ecx
        cmpl $1000, %ecx
        #FP_REG_KILL
        jne .LBB_foo_1  # no_exit

SSE2:
        addsd (%eax,%ecx,8), %xmm0
        incl %ecx
        cmpl $1000, %ecx
        #FP_REG_KILL
        jne .LBB_foo_1  # no_exit

llvm-svn: 22340

working.  The instruction selector changes will hopefully be coming later
this week once they are debugged.  This is necessary to support the darwin
x86 FP model, and is recommended by intel as the replacement for x87.  As
a bonus, the register allocator knows how to deal with these registers
across basic blocks, unliky the FP stackifier.  This leads to significantly
better codegen in several cases.

llvm-svn: 22300

sorta-pseudo-instruction

llvm-svn: 22042

llvm-svn: 22040

llvm-svn: 22036

llvm-svn: 21945

llvm-svn: 21829

llvm-svn: 21608

llvm-svn: 21106

llvm-svn: 21006

llvm-svn: 20343

llvm-svn: 19690

llvm-svn: 19687

This allows us to generate this:

foo:
        mov %EAX, DWORD PTR [%ESP + 4]
        mov %EDX, DWORD PTR [%ESP + 8]
        shld %EDX, %EDX, 2
        shl %EAX, 2
        ret

instead of this:

foo:
        mov %EAX, DWORD PTR [%ESP + 4]
        mov %ECX, DWORD PTR [%ESP + 8]
        mov %EDX, %EAX
        shrd %EDX, %ECX, 30
        shl %EAX, 2
        ret

Note the magically transmogrifying immediate.

llvm-svn: 19686

llvm-svn: 19437

llvm-svn: 19264

1. Add new instructions for checking parity flags: JP, JNP, SETP, SETNP.
2. Set the isCommutable and isPromotableTo3Address bits on several
   instructions.

llvm-svn: 19246

It's stosl (l for long == 32 bit).

llvm-svn: 17658

the JIT had last night.

llvm-svn: 16766

llvm-svn: 16759

llvm-svn: 16645

old and broken AT&T syntax assemblers.  The problem with this hack is that
*SOME* forms of the fdiv and fsub instructions have the 'r' bit inverted.
This was a real pain to figure out, but is trivially easy to support: thus
we are now bug compatible with gas and gcc.

llvm-svn: 16644

llvm-svn: 16642

llvm-svn: 16641

llvm-svn: 16640

hopefully lead to the death of the 'GasBugWorkaroundEmitter'.  This also
includes changes to wrap the whole file to 80 columns! Woot! :)

Note that the AT&T style output has not been tested at all.

llvm-svn: 16638

FpSETRESULT.

llvm-svn: 16247

value is returned in that register. The pseudo instructions
FpGETRESULT and FpSETRESULT shold also have an implicity use and def
of ST0 repsecitvely.

llvm-svn: 16246

old asmprinter.

llvm-svn: 15660

llvm-svn: 15657

Eliminate the FPI*m classes, converting them to use FPI instead.

llvm-svn: 15655

llvm-svn: 15653

llvm-svn: 15652

llvm-svn: 15651

asmprintergeneration

llvm-svn: 15650

Start asmprintergen'ifying machine instrs with memory operands.

llvm-svn: 15646

X86InstrInfo.td into 80 columns

llvm-svn: 15629

llvm-svn: 15628