"-mattr=+vfp3" is specified. However, this will not work for hardware that
only supports 16 registers.  Add a new flag to support -"mattr=+vfp3,+d16".
Patch by Jan Voung!

llvm-svn: 116310

address that we've looked through.

Fixes compilation problems in tramp3d from earlier patch.

llvm-svn: 116296

llvm-svn: 116284

llvm-svn: 116266

register operand.

llvm-svn: 116259

Added ARM specific ELF section types.
Added AttributesSection to ARMElfTargetObject
First step in unifying .cpu assembly tag with ELF/.o
llc now asserts on actual ELF emission on -filetype=obj :-)

llvm-svn: 116257

llvm-svn: 116251

llvm-svn: 116249

llvm-svn: 116240

leave custom lowerings for later.

Fixes some nightly tests.

llvm-svn: 116232

virtual registers for those stores since RegAllocFast requires that each live
physreg only be used once.

This fixes PR8357.

llvm-svn: 116222

llvm-svn: 116220

llvm-svn: 116218

Also don't use fast-isel on non-darwin since it's untested.

llvm-svn: 116217

llvm-svn: 116214

matching in tblgen to do the predicate operand.

llvm-svn: 116213

llvm-svn: 116212

llvm-svn: 116201

llvm-svn: 116198

llvm-svn: 116197

llvm-svn: 116196

llvm-svn: 116195

llvm-svn: 116194

it comes back, it will be largely a rewrite, so keeping the old codebase
in tree isn't helping anyone.

llvm-svn: 116190

llvm-svn: 116188

llvm-svn: 116177

llvm-svn: 116174

llvm-svn: 116173

alignment for PPC32/64, avoiding some masking operations.

llvm-gcc expands vaarg inline instead of using the instruction
so it has never hit this.

llvm-svn: 116168

llvm-svn: 116149

llvm-svn: 116143

llvm-svn: 116140

llvm-svn: 116136

llvm-svn: 116135

1. Cortex-A8 load / store multiplies can only issue on ALU0.
2. Eliminate A8_Issue, A8_LSPipe will correctly limit the load / store issues.
3. Correctly model all vld1 and vld2 variants.

llvm-svn: 116134

before decrementing. <rdar://problem/8529919>

llvm-svn: 116126

the add/or xform.  The JIT isn't mcized yet, boo.

This fixes Olden/voronoi, bh and a ton of other stuff that
uses the jit.

llvm-svn: 116125

llvm-svn: 116124

llvm-svn: 116123

concept level stuff at this point, but it is generally working for those
instructions that know how to map the operands.

This patch fills in the register operands for add/sub/or/etc instructions
and adds the conditional execution predicate encoding.

llvm-svn: 116112