llvm-svn: 133944

The index stored in the RegDefIter is one after the current index.  When getting the index, decrement it so that it points to the current element.  Fixes an off-by-one bug encountered when trying to make use of MVT::untyped.

llvm-svn: 133923

Removed the check that peeks past EXTRA_SUBREG, which I don't think
makes sense any more. Intead treat it as a normal register def. No
significant affect on x86 or ARM benchmarks.

llvm-svn: 133917

Patch by Sanjoy Das!

llvm-svn: 133910

Both become <earlyclobber> defs on the INLINEASM MachineInstr, but we
now use two different asm operand kinds.

The new Kind_Clobber is treated identically to the old
Kind_RegDefEarlyClobber for now, but x87 floating point stack inline
assembly does care about the difference.

This will pop a register off the stack:

  asm("fstp %st" : : "t"(x) : "st");

While this will pop the input and push an output:

  asm("fst %st" : "=&t"(r) : "t"(x));

We need to know if ST0 was a clobber or an output operand, and we can't
depend on <dead> flags for that.

llvm-svn: 133902

The INLINEASM MachineInstrs have an immediate operand describing each
original inline asm operand. Decode the bits in MachineInstr::print() so
it is easier to read:

  INLINEASM <es:rorq $1,$0>, $0:[regdef], %vreg0<def>, %vreg1<def>, $1:[imm], 1, $2:[reguse] [tiedto:$0], %vreg2, %vreg3, $3:[regdef-ec], %EFLAGS<earlyclobber,imp-def>

llvm-svn: 133901

llvm-svn: 133900

remove the analysis group.

llvm-svn: 133899

llvm-svn: 133897

llvm-svn: 133896

llvm-svn: 133895

llvm-svn: 133886

The scheduler needs to be aware on the existence of untyped nodes when it performs type propagation for EXTRACT_SUBREG.

llvm-svn: 133838

llvm-svn: 133821

llvm-svn: 133798

we cannot duplicate to every predecessor.

llvm-svn: 133797

llvm-svn: 133793

target machine from those that are only needed by codegen. The goal is to
sink the essential target description into MC layer so we can start building
MC based tools without needing to link in the entire codegen.

First step is to refactor TargetRegisterInfo. This patch added a base class
MCRegisterInfo which TargetRegisterInfo is derived from. Changed TableGen to
separate register description from the rest of the stuff.

llvm-svn: 133782

supports compact unwind info instead of having a separate flag indicating this.

llvm-svn: 133685

register allocation if it has a indirectbr or if we can duplicate it to
every predecessor.

This fixes the SingleSource/Benchmarks/Shootout-C++/matrix.cpp regression but
keeps the previous improvements to sunspider.

llvm-svn: 133682

llvm-svn: 133662

don't remove blocks that have their address taken.

llvm-svn: 133659

If the linker supports it, this will hold the CIE and FDE information in a
compact format. The implementation of the compact unwinding emission is coming
soon.

llvm-svn: 133658

Specifically, gcc.c-torture/compile/pr21356.c.

llvm-svn: 133646

is larger than the sum of the elements (including per-element padding).

llvm-svn: 133631

that takes an ArrayRef.

llvm-svn: 133615

be one with only one unconditional branch and no phis. Duplicating the phis in this case
is possible, but requeres liveness analysis or breaking edges.

llvm-svn: 133607

llvm-svn: 133569

llvm-svn: 133567

llvm-svn: 133561

There could be more than one DBG_VALUE instructions for variables where all of them have offset based on one register.

llvm-svn: 133560

explanation of what the EH table describes.

llvm-svn: 133559

1. (((x) & 0xFF00) >> 8) | (((x) & 0x00FF) << 8)
   => (bswap x) >> 16
2. ((x&0xff)<<8)|((x&0xff00)>>8)|((x&0xff000000)>>8)|((x&0x00ff0000)<<8))
   => (rotl (bswap x) 16)

This allows us to eliminate most of the def : Pat patterns for ARM rev16
revsh instructions. It catches many more cases for ARM and x86.

rdar://9609108

llvm-svn: 133503

llvm-svn: 133446

* Don't introduce a duplicated bb in the CFG
* When making a branch unconditional, clear the PredCond array so that it
  is really unconditional.

llvm-svn: 133432

dragonegg buildbots back to life.  Original commit message:
Teach early dup how to duplicate basic blocks with one successor and only phi instructions
into more complex blocks.

llvm-svn: 133430

source vector type is to be split while the target vector is to be promoted.
(eg: <4 x i64> -> <4 x i8> )

llvm-svn: 133424

Fix MSVC build. next() function already exists in the MSVC headers. This create a overload conflict. Make sure we pick up the llvm one.

llvm-svn: 133416

into more complex blocks.

llvm-svn: 133415

all over the place in different styles and variants.  Standardize on two
preferred entrypoints: one that takes a StructType and ArrayRef, and one that
takes StructType and varargs.

In cases where there isn't a struct type convenient, we now add a
ConstantStruct::getAnon method (whose name will make more sense after a few
more patches land).  

It would be "really really nice" if the ConstantStruct::get and 
ConstantVector::get methods didn't make temporary std::vectors.

llvm-svn: 133412