Add a RetVT parameter to emitted FastISel methods, so that we will be able to pass the desired return
type down.  This is not currently used.

llvm-svn: 55345

Deepen the map structure tablegen uses to compute FastISel patterns, in preparation for having patterns
with return types that differ from their input types.  This is not yet used.

llvm-svn: 55344

bitcast of constants in fast isel.

llvm-svn: 55325

process up to a higher level. This allows FastISel to leverage
more of SelectionDAGISel's infastructure, such as updating Machine
PHI nodes.

Also, implement transitioning from SDISel back to FastISel in
the middle of a block, so it's now possible to go back and
forth. This allows FastISel to hand individual CallInsts and other
complicated things off to SDISel to handle, while handling the rest
of the block itself.

To help support this, reorganize the SelectionDAG class so that it
is allocated once and reused throughout a function, instead of
being completely reallocated for each block.

llvm-svn: 55219

llvm-svn: 55157

and use it in FastISelEmitter.cpp, and make FastISel
subtarget aware. Among other things, this lets it work
properly on x86 targets that don't have SSE, where it
successfully selects x87 instructions.

llvm-svn: 55156

llvm-svn: 55099

llvm-svn: 55096

llvm-svn: 55093

llvm-svn: 55080

namespace out of the isel emitters and into common code.

llvm-svn: 55079

class hold a MachineRegisterInfo member, and make the
MachineBasicBlock be passed in to SelectInstructions rather
than the FastISel constructor.

llvm-svn: 55076

llvm-svn: 55034

register class.

llvm-svn: 55008

helper function.

llvm-svn: 55007

llvm-svn: 55004

llvm-svn: 55003

FastISel doesn't support yet.

llvm-svn: 55002

llvm-svn: 54998

llvm-svn: 54997

llvm-svn: 54996

llvm-svn: 54971

subregister query, and by increasing the size of the subregister hashtable so
that there are fewer collisions.

llvm-svn: 54781

llvm-svn: 54756

the comments in FastISelEmitter.cpp for details on what this is.
This is currently experimental and unusable.

llvm-svn: 54751

llvm-svn: 54750

llvm-svn: 54630

llvm-svn: 54386

to different address spaces.  This alters the naming scheme for those
intrinsics, e.g., atomic.load.add.i32 => atomic.load.add.i32.p0i32

llvm-svn: 54195

llvm-svn: 54137

llvm-svn: 54128

they appear in words. This would cause things like the "128" in "VR128"
to be highlighted. This patch fixes the highlighting by only recognizing 
constants when they have word breaks around them.'

Patch by Stefanus Du Toit!

llvm-svn: 53944

llvm-svn: 53860

replacement of multiple values. This is slightly more efficient
than doing multiple ReplaceAllUsesOfValueWith calls, and theoretically
could be optimized even further. However, an important property of this
new function is that it handles the case where the source value set and
destination value set overlap. This makes it feasible for isel to use
SelectNodeTo in many very common cases, which is advantageous because
SelectNodeTo avoids a temporary node and it doesn't require CSEMap
updates for users of values that don't change position.

Revamp MorphNodeTo, which is what does all the work of SelectNodeTo, to
handle operand lists more efficiently, and to correctly handle a number
of corner cases to which its new wider use exposes it.

This commit also includes a change to the encoding of post-isel opcodes
in SDNodes; now instead of being sandwiched between the target-independent
pre-isel opcodes and the target-dependent pre-isel opcodes, post-isel
opcodes are now represented as negative values. This makes it possible
to test if an opcode is pre-isel or post-isel without having to know
the size of the current target's post-isel instruction set.

These changes speed up llc overall by 3% and reduce memory usage by 10%
on the InstructionCombining.cpp testcase with -fast and -regalloc=local.

llvm-svn: 53728

Update to build_llvm. Don't output a floating point number for the version.

llvm-svn: 53484

TargetRegisterDesc::Name field is the same as the abstract register name. There is no need for targets to specify register names in addition to their AsmName's.

llvm-svn: 53207

getTargetNode and SelectNodeTo to reduce duplication, and to
make some of the getTargetNode code available to SelectNodeTo.
Use SelectNodeTo instead of getTargetNode in several new
interesting cases, as it mutates nodes in place instead of
creating new ones.

This triggers some scheduling behavior differences due to nodes
being presented to the scheduler in a different order. Some of the
arbitrary scheduling decisions it makes are now arbitrarily made
differently. This is visible in CodeGen/PowerPC/LargeAbsoluteAddr.ll,
where a trivial scheduling difference led to a trivial register
allocation difference.

llvm-svn: 53203

llvm-svn: 53179

llvm-svn: 53096

SelectionDAG::SelectNodeTo in the instruction selector. This
updates existing nodes in place instead of creating new ones.

Go back to selecting ISD::DBG_LABEL nodes into
TargetInstrInfo::DBG_LABEL nodes instead of leaving them
unselected, now that SelectNodeTo allows us to update them
in place.

llvm-svn: 53057