when we fail to place all the blocks of a loop. Currently this is
happening for unnatural loops, and this logic helps more immediately
point to the problem.

llvm-svn: 144504

The old naming scheme (load/use/def/store) can be traced back to an old
linear scan article, but the names don't match how slots are actually
used.

The load and store slots are not needed after the deferred spill code
insertion framework was deleted.

The use and def slots don't make any sense because we are using
half-open intervals as is customary in C code, but the names suggest
closed intervals.  In reality, these slots were used to distinguish
early-clobber defs from normal defs.

The new naming scheme also has 4 slots, but the names match how the
slots are really used.  This is a purely mechanical renaming, but some
of the code makes a lot more sense now.

llvm-svn: 144503

llvm-svn: 144502

branches that also may involve fallthrough. In the case of blocks with
no fallthrough, we can still re-order the blocks profitably. For example
instruction decoding will in some cases continue past an indirect jump,
making laying out its most likely successor there profitable.

Note, no test case. I don't know how to write a test case that exercises
this logic, but it matches the described desired semantics in
discussions with Jakob and others. If anyone has a nice example of IR
that will trigger this, that would be lovely.

Also note, there are still assertion failures in real world code with
this. I'm digging into those next, now that I know this isn't the cause.

llvm-svn: 144499

llvm-svn: 144498

llvm-svn: 144497

llvm-svn: 144496

second algorithm, but only loosely. It is more heavily based on the last
discussion I had with Andy. It continues to walk from the inner-most
loop outward, but there is a key difference. With this algorithm we
ensure that as we visit each loop, the entire loop is merged into
a single chain. At the end, the entire function is treated as a "loop",
and merged into a single chain. This chain forms the desired sequence of
blocks within the function. Switching to a single algorithm removes my
biggest problem with the previous approaches -- they had different
behavior depending on which system triggered the layout. Now there is
exactly one algorithm and one basis for the decision making.

The other key difference is how the chain is formed. This is based
heavily on the idea Andy mentioned of keeping a worklist of blocks that
are viable layout successors based on the CFG. Having this set allows us
to consistently select the best layout successor for each block. It is
expensive though.

The code here remains very rough. There is a lot that needs to be done
to clean up the code, and to make the runtime cost of this pass much
lower. Very much WIP, but this was a giant chunk of code and I'd rather
folks see it sooner than later. Everything remains behind a flag of
course.

I've added a couple of tests to exercise the issues that this iteration
was motivated by: loop structure preservation. I've also fixed one test
that was exhibiting the broken behavior of the previous version.

llvm-svn: 144495

The order in which the predicate is added differs between Thumb and ARM mode.  Fix predicate when in ARM mode and restore SelectIntrinsicCall.

llvm-svn: 144494

llvm-svn: 144492

llvm-svn: 144490

SimplifyAddress to handle either a 12-bit unsigned offset or the ARM +/-imm8
offsets (addressing mode 3).  This enables a load followed by an integer 
extend to be folded into a single load.

For example:
ldrb r1, [r0]       ldrb r1, [r0]
uxtb r2, r1     =>
mov  r3, r2         mov  r3, r1

llvm-svn: 144488

llvm-svn: 144487

This thing is looking a lot like a virtual register map now.

llvm-svn: 144486

Nobody cared, StackSlotColoring scans the instructions to find used stack
slots.

llvm-svn: 144485

Most of this stuff was supporting the old deferred spill code insertion
mechanism.  Modern spillers just edit machine code in place.

llvm-svn: 144484

The information was only used by the register allocator in
StackSlotColoring.

llvm-svn: 144482

It was off by default.

The new register allocators don't have the problems that made it
necessary to reallocate registers during stack slot coloring.

llvm-svn: 144481

And there was much rejoicing.

llvm-svn: 144480

The very complicated VirtRegRewriter is going away.

llvm-svn: 144479

This is dead code, all register allocators use InlineSpiller.

llvm-svn: 144478

The current register allocators all use the inline spiller.

llvm-svn: 144477

It is worth noting that the old spiller would split live ranges around
basic blocks. The new spiller doesn't do that.

PBQP should do its own live range splitting with
SplitEditor::splitSingleBlock() if desired.  See
RAGreedy::tryBlockSplit().

llvm-svn: 144476

RegAllocGreedy has been the default for six months now.

Deleting RegAllocLinearScan makes it possible to also delete
VirtRegRewriter and clean up the spiller code.

llvm-svn: 144475

Counting the number of occurences of each opcode is not a useful test.

llvm-svn: 144474

Or maybe we are just getting lucky.

llvm-svn: 144473

llvm-svn: 144472

Filed PR11364 to track the problem.  Should the register allocator
eliminate dead code?

llvm-svn: 144471

This test was committed with a bugfix to RemoveCopyByCommutingDef, but
that optimization is no longer triggered by this test.

llvm-svn: 144470

This test is for a very specific LocalRewriter bug.  LocalRewriter is
going away.

llvm-svn: 144469

I don't think this test does what is was supposed to do, and
LocalRewriter is going away anyway.

llvm-svn: 144463

llvm-svn: 144462

llvm-svn: 144461

llvm-svn: 144460

This test doesn't expose the issue with RAGreedy.

I filed PR11363 to track the missing InlineSpiller feature.

llvm-svn: 144459

The test is checking that the output doesn't contains any 'mov '
strings. It does contain movl, though.

llvm-svn: 144458

Add more AVX2 shift lowering support. Move AVX2 variable shift to use patterns instead of custom lowering code.

llvm-svn: 144457

llvm-svn: 144454

llvm-svn: 144453

llvm-svn: 144452