No functionality change.

llvm-svn: 152927

llvm-svn: 152016

llvm-svn: 152001

llvm-svn: 151996

llvm-svn: 151223

Affect on SD scheduling and postRA scheduling:
Printing the DAG will display the nodes in top-down topological order.
This matches the order within the MBB and makes my life much easier in general.

Affect on misched:
We don't need to track virtual register uses at all. This is awesome.
I also intend to rely on the SUnit ID as a topo-sort index. So if A < B then we cannot have an edge B -> A.

llvm-svn: 151135

opportunities that only present themselves after late optimizations
such as tail duplication .e.g.
## BB#1:
        movl    %eax, %ecx
        movl    %ecx, %eax
        ret

The register allocator also leaves some of them around (due to false
dep between copies from phi-elimination, etc.)

This required some changes in codegen passes. Post-ra scheduler and the
pseudo-instruction expansion passes have been moved after branch folding
and tail merging. They were before branch folding before because it did
not always update block livein's. That's fixed now. The pass change makes
independently since we want to properly schedule instructions after
branch folding / tail duplication.

rdar://10428165
rdar://10640363

llvm-svn: 147716

generator to it. For non-bundle instructions, these behave exactly the same
as the MC layer API.

For properties like mayLoad / mayStore, look into the bundle and if any of the
bundled instructions has the property it would return true.
For properties like isPredicable, only return true if *all* of the bundled
instructions have the property.
For properties like canFoldAsLoad, isCompare, conservatively return false for
bundles.

llvm-svn: 146026

llvm-svn: 133944

No functional change was intended.

llvm-svn: 133202

llvm-svn: 132487

Avoid using the same register for two def operands or and earlyclobber
def and use operand. This fixes PR8986 and improves on the prior fix
for rdar://problem/8959122.

llvm-svn: 125089

<rdar://problem/8959122> illegal register operands for UMULL instruction in cfrac nightly test
I'm stil working on a unit test, but the case is:
rx = movcc rx, r3
r2 = ldr
r2, r3 = umull r2, r2

The anti-dep breaker should not convert this into an illegal instruction:
r2, r2 = umull

llvm-svn: 124932

breaker needs to check all definitions of the antidepenent register to
avoid multiple defs of the same new register.

llvm-svn: 118032

scheduling change in svn 115121.  The CriticalAntiDepBreaker had bad
liveness information.  It was calculating the KillIndices for one scheduling
region in a basic block, rescheduling that region so the KillIndices were
no longer valid, and then using those wrong KillIndices to make decisions
for the next scheduling region.  I've not been able to reduce a small
testcase for this.  Radar 8502534.

llvm-svn: 115400

llvm-svn: 113653

llvm-svn: 112832

llvm-svn: 109468

make sure to allocate enough space in the std::vector.

llvm-svn: 108449

llvm-svn: 108419

get *very* large, but we only need it to be the size of thenumber of pregs.

llvm-svn: 108411

Make post-ra scheduling, anti-dep breaking, and register scavenger (conservatively) aware of predicated instructions. This enables ARM to move if-conversion before post-ra scheduler.

llvm-svn: 106091

for debug information.

llvm-svn: 105324

llvm-svn: 105300

llvm-svn: 103807

and End arguments by-value rather than by-reference.

llvm-svn: 101830

llvm-svn: 97765

multiple register definitions.

llvm-svn: 92864

llvm-svn: 92837

Change errs() to dbgs().

llvm-svn: 92490

llvm-svn: 90970

Remove some old experimental code that is no longer needed. Remove additional, speculative scheduling pass as its cost did not translate into significant performance improvement. Minor tweaks.

llvm-svn: 89471

Do a scheduling pass ignoring anti-dependencies to identify candidate registers that should be renamed.

llvm-svn: 85939

llvm-svn: 85127