llvm-svn: 134030

sink them into MC layer.
- Added MCInstrInfo, which captures the tablegen generated static data. Chang
TargetInstrInfo so it's based off MCInstrInfo.

llvm-svn: 134021

llvm-svn: 134013

llvm-svn: 133981

llvm-svn: 133978

llvm-svn: 133967

llvm-svn: 133962

During bottom up fast-isel, instructions emitted to materalize registers are at top of basic block and do not have debug location. This may misguide debugger while entering the basic block and sometimes debugger provides semi useful view of current location to developer by picking up previous known location as current location. Assign a sensible location to the first instruction in a basic block, if it does not have one location derived from source file, so that debugger can provide meaningful user experience to developers in edge cases.

llvm-svn: 133953

llvm-svn: 133944

The index stored in the RegDefIter is one after the current index.  When getting the index, decrement it so that it points to the current element.  Fixes an off-by-one bug encountered when trying to make use of MVT::untyped.

llvm-svn: 133923

Removed the check that peeks past EXTRA_SUBREG, which I don't think
makes sense any more. Intead treat it as a normal register def. No
significant affect on x86 or ARM benchmarks.

llvm-svn: 133917

Patch by Sanjoy Das!

llvm-svn: 133910

Both become <earlyclobber> defs on the INLINEASM MachineInstr, but we
now use two different asm operand kinds.

The new Kind_Clobber is treated identically to the old
Kind_RegDefEarlyClobber for now, but x87 floating point stack inline
assembly does care about the difference.

This will pop a register off the stack:

  asm("fstp %st" : : "t"(x) : "st");

While this will pop the input and push an output:

  asm("fst %st" : "=&t"(r) : "t"(x));

We need to know if ST0 was a clobber or an output operand, and we can't
depend on <dead> flags for that.

llvm-svn: 133902

The INLINEASM MachineInstrs have an immediate operand describing each
original inline asm operand. Decode the bits in MachineInstr::print() so
it is easier to read:

  INLINEASM <es:rorq $1,$0>, $0:[regdef], %vreg0<def>, %vreg1<def>, $1:[imm], 1, $2:[reguse] [tiedto:$0], %vreg2, %vreg3, $3:[regdef-ec], %EFLAGS<earlyclobber,imp-def>

llvm-svn: 133901

llvm-svn: 133900

remove the analysis group.

llvm-svn: 133899

llvm-svn: 133897

llvm-svn: 133896

llvm-svn: 133895

llvm-svn: 133886

The scheduler needs to be aware on the existence of untyped nodes when it performs type propagation for EXTRACT_SUBREG.

llvm-svn: 133838

llvm-svn: 133821

llvm-svn: 133798

we cannot duplicate to every predecessor.

llvm-svn: 133797

llvm-svn: 133793

target machine from those that are only needed by codegen. The goal is to
sink the essential target description into MC layer so we can start building
MC based tools without needing to link in the entire codegen.

First step is to refactor TargetRegisterInfo. This patch added a base class
MCRegisterInfo which TargetRegisterInfo is derived from. Changed TableGen to
separate register description from the rest of the stuff.

llvm-svn: 133782

supports compact unwind info instead of having a separate flag indicating this.

llvm-svn: 133685

register allocation if it has a indirectbr or if we can duplicate it to
every predecessor.

This fixes the SingleSource/Benchmarks/Shootout-C++/matrix.cpp regression but
keeps the previous improvements to sunspider.

llvm-svn: 133682

llvm-svn: 133662

don't remove blocks that have their address taken.

llvm-svn: 133659

If the linker supports it, this will hold the CIE and FDE information in a
compact format. The implementation of the compact unwinding emission is coming
soon.

llvm-svn: 133658

Specifically, gcc.c-torture/compile/pr21356.c.

llvm-svn: 133646

is larger than the sum of the elements (including per-element padding).

llvm-svn: 133631

that takes an ArrayRef.

llvm-svn: 133615

be one with only one unconditional branch and no phis. Duplicating the phis in this case
is possible, but requeres liveness analysis or breaking edges.

llvm-svn: 133607

llvm-svn: 133569

llvm-svn: 133567

llvm-svn: 133561

There could be more than one DBG_VALUE instructions for variables where all of them have offset based on one register.

llvm-svn: 133560

explanation of what the EH table describes.

llvm-svn: 133559