Fix an issue where a use might be selected before a def, and then we didn't respect the pre-chosen vreg
assignment when selecting the def.  This is the naive solution to the problem: insert a copy to the pre-chosen
vreg.  Other solutions might be preferable, such as:
  1) Passing the dest reg into FastEmit_.  However, this would require the higher level code to know about reg classes, which they don't currently.
  2) Selecting blocks in reverse postorder.  This has some compile time cost for computing the order, and we'd need to measure its impact.

llvm-svn: 55555

llvm-svn: 55554

llvm-svn: 55553

llvm-svn: 55552

llvm-svn: 55551

llvm-svn: 55549

llvm-svn: 55548

llvm-svn: 55546

llvm-svn: 55545

llvm-svn: 55542

%4 = add ...

instead of:

add ...    ; 4

This makes opt -print-cfg output actually usable and makes .ll files
generally easier to read.  This fixes PR2480

llvm-svn: 55541

nameless values, such as:

%3 = add i32 4, 2

This fixes the first half of PR2480

llvm-svn: 55539

llvm-svn: 55533

llvm-svn: 55531

llvm-svn: 55530

llvm-svn: 55528

llvm-svn: 55521

llvm-svn: 55518

llvm-svn: 55512

llvm-svn: 55511

llvm-svn: 55508

whose darwin code was written after the ability to dynamically register frames,
we need to do special hacks to make things work.

llvm-svn: 55507

llvm-svn: 55504

llvm-svn: 55500

In lowering SELECT_CC, removed cases where we can't flip the true and false when the compare value has a NaN

llvm-svn: 55499

its work by putting all nodes in the worklist, requiring a big
dynamic allocation. Now, DAGCombiner just iterates over the AllNodes
list and maintains a worklist for nodes that are newly created or
need to be revisited. This allows the worklist to stay small in most
cases, so it can be a SmallVector.

This has the side effect of making DAGCombine not miss a folding
opportunity in alloca-align-rounding.ll.

llvm-svn: 55498

SelectionDAGLowering instead of being in an anonymous namespace.
This fixes warnings about SelectionDAGLowering having fields
using anonymous namespaces.

llvm-svn: 55497

were being emitted after the first instructions of the entry block.

llvm-svn: 55496

llvm-svn: 55486

llvm-svn: 55483

Hook up support for fast-isel of trunc instructions, using the newly working support for EXTRACT_SUBREG.

llvm-svn: 55482

llvm-svn: 55478

FastEmitInst_extractsubreg doesn't need to be passed the register class.  It can get it from MachineRegisterInfo instead.

llvm-svn: 55476

Benchmarks/sim/sim, and others on x86-64.

llvm-svn: 55475

llvm-svn: 55471

If a copy isn't coalesced, but its src is defined by trivial computation. Re-materialize the src to replace the copy.

llvm-svn: 55467

llvm-svn: 55466

for operands: rdar://6179606.  no testcase, because I can't write
a .ll file that is this broken ;-)

llvm-svn: 55460

Prakash Prabhu!

llvm-svn: 55458

ATOMIC_LOAD_ADD_{8,16,32,64} instead of ATOMIC_LOAD_ADD.
Increased the Hardcoded Constant OpActionsCapacity to match.
Large but boring; no functional change.

This is to support partial-word atomics on ppc; i8 is
not a valid type there, so by the time we get to lowering, the
ATOMIC_LOAD nodes looks the same whether the type was i8 or i32.
The information can be added to the AtomicSDNode, but that is the
largest SDNode; I don't fully understand the SDNode allocation,
but it is sensitive to the largest node size, so increasing
that must be bad.  This is the alternative.

llvm-svn: 55457