llvm-svn: 186811

After Ulrich's r180677 (thanks!) TableGen is intelligent enough to
handle tied constraints involving complex operands properly, so
virtually all of the ARM custom converters are now unnecessary.

llvm-svn: 186810

llvm-svn: 186809

deallocation functions.

llvm-svn: 186798

llvm-svn: 186787

indirect branches correctly. Under some circumstances, this led to the deletion
of basic blocks that were the destination of indirect branches. In that case it
left indirect branches to nowhere in the code.

This patch replaces, and is more general than either of the previous fixes for
indirect-branch-analysis issues, r181161 and r186461.

For other branches (not indirect) this refactor should have *almost* identical
behavior to the previous version. There are some corner cases where this
refactor is able to analyze blocks that the previous version could not (e.g.
this necessitated the update to thumb2-ifcvt2.ll). 

<rdar://problem/14464830>

llvm-svn: 186735

llvm-svn: 186725

llvm-svn: 186724

llvm-svn: 186723

llvm-svn: 186692

Follows the same lines as r186686, but much more limited, since we only
use ADD LOGICAL for multi-i64 additions.

llvm-svn: 186689

llvm-svn: 186688

I did these as a separate patch because it uses a slightly different
form of RIE layout.

llvm-svn: 186687

The testsuite changes follow the same lines as for r186683.

llvm-svn: 186686

Like r186683, but for 64 bits.

llvm-svn: 186685

The atomic tests assume the two-operand forms, so I've restricted them to z10.

Running and-01.ll, or-01.ll and xor-01.ll for z196 as well as z10 shows why
using convertToThreeAddress() is better than exposing the three-operand forms
first and then converting back to two operands where possible (which is what
I'd originally tried).  Using the three-operand form first stops us from
taking advantage of NG, OG and XG for spills.

llvm-svn: 186683

See A8.8.127 in ARM DDI 0406C.b.

Related to <rdar://problem/14403733>.

llvm-svn: 186682

This patch uses the instructions added in r186680 for codegen.

llvm-svn: 186681

This first step just adds definitions for SLLK, SRLK and SRAK.
The next patch will actually make use of them during codegen.

insn-bad.s tests that some form of error is reported when using these
instructions on z10.  More work is needed to get the "instruction requires:
distinct-ops" that we'd ideally like, so I've stubbed that part out for now.
I'll come back and make it mandatory once the necessary changes are in.

llvm-svn: 186680

No functionality change.

llvm-svn: 186642

PLI requires both the Thumb2 and the ARMv7 feature.

Related to <rdar://problem/14403733>.

llvm-svn: 186620

https://bugs.freedesktop.org/show_bug.cgi?id=66175

llvm-svn: 186616

llvm-svn: 186615

llvm-svn: 186614

llvm-svn: 186613

llvm-svn: 186576

llvm-svn: 186574

This should be the last of the R.SBG patches for now.

llvm-svn: 186573

Also, fix the namespace for two instructions that I missed previously.

llvm-svn: 186572

The original code only folded SRA into ROTATE ... SELECTED BITS
if there was no outer shift.  This patch splits out that check
and generalises it slightly.  The extra cases aren't really that
interesting, but this is paving the way for RNSBG support.

llvm-svn: 186571

Extend the previous R.SBG patches to handle XORs.

llvm-svn: 186570

In hindsight, using "RISBG" for something that can be any type of
R.SBG instruction was a bit confusing, so this renames it to RxSBG.
That might not be the best choice either, since there is an instruction
called RXSBG, but hopefully the lower-case letter stands out enough.

While there I fixed a couple of GNUisms that had crept in --
sorry about that!

llvm-svn: 186569

The N3VDIntnp pattern takes bits<5> and I gave it 6 bits.

Thanks to Jiangning Liu for spotting it!

llvm-svn: 186568

This patch extends mips register parsing methods to allow indexed register parsing. The corresponding test cases are added to the patch.

llvm-svn: 186567

llvm-svn: 186566

Support for dynamic stack alignments in the PPC backend has been unfinished, in
part because it depends on dynamic stack realignment (which I only just
recently implemented fully). Now we can also support dynamic allocas with
higher than the default target stack alignment (16 bytes).

In order to round-up the requested size to the maximum requested alignment, we
need an additional register to hold the rounded-up size. We're already using one
scavenged register to hold the previous stack-pointer value (which needs to be
stored with the signal-safe stdux update), and so when we have dynamic allocas
and a large alignment, we allocate two emergency spill slots for the scavenger.

llvm-svn: 186562

First, this changes the base-pointer implementation to remove an unnecessary
complication (and one that is incompatible with how builtin SjLj is
implemented): instead of using r31 as the base pointer when it is not needed as
a frame pointer, now the base pointer will always be r30 when needed.

Second, we introduce another pseudo register, BP, which is used just like the FP
pseudo register to refer to the base register before we know for certain what
register it will be.

Third, we now save BP into the jmp_buf, and restore r30 from that slot in
longjmp.  If the function that called setjmp did not use a base pointer, then
r30 will be overwritten by the setjmp-calling-function's restore code. FP
restoration (which is restored into r31) works the same way.

llvm-svn: 186545

llvm-svn: 186529

llvm-svn: 186528

This patch checks for valid mnemonics at the beginning of parseInstruction method, thus giving the user the right error message for non-existing instructions.

llvm-svn: 186512