Delete the 'name' field of all instructions that have asmformats.

llvm-svn: 15403

llvm-svn: 15398

llvm-svn: 15396

of in/out instructions (missing %'s on registers).

llvm-svn: 15393

This only really covers no-operand instructions so far.

llvm-svn: 15387

with an incremental approach rather than a revolutionary approach.

llvm-svn: 15379

or return intructions.

llvm-svn: 15356

llvm-svn: 14145

we can get rid of the FpUCOM/FpUCOMi pseudo instructions, which makes stuff simpler
and faster.

llvm-svn: 14144

twoarg cases.

llvm-svn: 14143

llvm-svn: 14140

llvm-svn: 12895

llvm-svn: 12855

I have unsaved emacs buffers, geeze...

llvm-svn: 12854

llvm-svn: 12853

llvm-svn: 12850

llvm-svn: 12838

InstSelectSimple.cpp:
  Change the checks for proper I/O port address size into an exit() instead
  of an assertion.  Assertions aren't used in Release builds, and handling
  this error should be graceful (not that this counts as graceful, but it's
  more graceful).

  Modified the generation of the IN/OUT instructions to have 0 arguments.
X86InstrInfo.td:
  Added the OpSize attribute to the 16 bit IN and OUT instructions.

llvm-svn: 12786

I/O port instructions on x86.  The specific code sequence is tailored to
the parameters and return value of the intrinsic call.
Added the ability for implicit defintions to be printed in the Instruction
Printer.
Added the ability for RawFrm instruction to print implict uses and
defintions with correct comma output.  This required adjustment to some
methods so that a leading comma would or would not be printed.

llvm-svn: 12782

llvm-svn: 12710

llvm-svn: 12682

llvm-svn: 12611

llvm-svn: 12607

that require the asmwriter to be extended (printing implicit uses before the
explicit operands)

llvm-svn: 12574

we never generated them

Make indentation a bit more consistent

llvm-svn: 12549

llvm-svn: 12424

llvm-svn: 12336

llvm-svn: 12254

llvm-svn: 12190

operand size is correctly specified.

llvm-svn: 11997

their names more decriptive. A name consists of the base name, a
default operand size followed by a character per operand with an
optional special size. For example:

ADD8rr -> add, 8-bit register, 8-bit register

IMUL16rmi -> imul, 16-bit register, 16-bit memory, 16-bit immediate

IMUL16rmi8 -> imul, 16-bit register, 16-bit memory, 8-bit immediate

MOVSX32rm16 -> movsx, 32-bit register, 16-bit memory

llvm-svn: 11995

llvm-svn: 11974

to denote this fact.

llvm-svn: 11972

denote this fact.

llvm-svn: 11971

parse. The name is now I (operand size)*. For example:

Im32 -> instruction with 32-bit memory operands.

Im16i8 -> instruction with 16-bit memory operands and 8 bit immediate
          operands.

llvm-svn: 11970

the size of the immediate and the memory operand on instructions that
use them. This resolves problems with instructions that take both a
memory and an immediate operand but their sizes differ (i.e. ADDmi32b).

llvm-svn: 11967

operands. The X86 backend doesn't handle them properly right now.

llvm-svn: 11944

llvm-svn: 11933

llvm-svn: 11932

an 8-bit immediate. So mark the shifts that take immediates as taking
an 8-bit argument. The rest with the implicit use of CL are marked
appropriately.

A bug still exists:

def SHLDmri32  : I2A8 <"shld", 0xA4, MRMDestMem>, TB;           // [mem32] <<= [mem32],R32 imm8

The immediate in the above instruction is 8-bit but the memory
reference is 32-bit. The printer prints this as an 8-bit reference
which confuses the assembler. Same with SHRDmri32.

llvm-svn: 11931