This patch adds Direct Object Emission support for I8 instructions: andi.b, bmnzi.b, bmzi.b, bseli.b, nori.b, ori.b, shf.{b,h,w} and xori.b.


Patch by Matheus Almeida

llvm-svn: 191688

This patch adds Direct Object Emission support for I5 instructions: addvi.{b,h,w,d}, ceqi.{b,h,w,d}, clei_s.{b,h,w,d}, clei_u.{b,h,w,d}, clti_s.{b,h,w,d}, clti_u.{b,h,w,d}, maxi_s.{b,h,w,d}, maxi_u.{b,h,w,d}, mini_s.{b,h,w,d}, mini_u.{b,h,w,d}, subvi.{b,h,w,d}.


Patch by Matheus Almeida

llvm-svn: 191687

Fix some LLVM Coding Standards violations.

No changes in functionality.

llvm-svn: 191686

This patch adds Direct Object Emission support for 2R instructions: nloc.{b,h,w}, nlzc.{b,h,w}, pcnt.{b,w,d}.  


Patch by Matheus Almeida

llvm-svn: 191685

 and not an MSA register

Patch by Matheus Almeida

llvm-svn: 191684

llvm-svn: 191683

llvm-svn: 191682

Differential Revision: http://llvm-reviews.chandlerc.com/D1751

llvm-svn: 191681

Patch by Richard Sandiford.

llvm-svn: 191680

This reverts commit r191670.

It was causing build failures on the msvc bots:

http://bb.pgr.jp/builders/ninja-clang-i686-msc17-R/builds/5166/steps/compile/logs/stdio

llvm-svn: 191679

[ARM] Assembler: ARM LDRD with writeback requires the base register to be different from the destination registers.

See ARM ARM A8.8.72.

Violating this constraint results in unpredictable behavior.

llvm-svn: 191678

Those writes really need two/three uops.

llvm-svn: 191677

llvm-svn: 191676

llvm-svn: 191675

Defines away the issue where cast<Instruction> would fail because constant
folding happened. Also slightly cleaner.

llvm-svn: 191674

Inspired by the object from the SLPVectorizer. This found a minor bug in the
debug loc restoration in the vectorizer where the location of a following
instruction was attached instead of the location from the original instruction.

llvm-svn: 191673

They don't depend on the templated stuff.

llvm-svn: 191672

For targets that have instruction itineraries this means no change. Targets
that move over to the new schedule model will use be able the new schedule
module for instruction latencies in the if-converter (the logic is such that if
there is no itineary we will use the new sched model for the latencies).

Before, we queried "TTI->getInstructionLatency()" for the instruction latency
and the extra prediction cost. Now, we query the TargetSchedule abstraction for
the instruction latency and TargetInstrInfo for the extra predictation cost. The
TargetSchedule abstraction will internally call "TTI->getInstructionLatency" if
an itinerary exists, otherwise it will use the new schedule model.

ATTENTION: Out of tree targets!

(I will also send out an email later to LLVMDev)

This means, if your target implements

 unsigned getInstrLatency(const InstrItineraryData *ItinData,
                          const MachineInstr *MI,
                          unsigned *PredCost);

and returns a value for "PredCost", you now also need to implement

 unsigned getPredictationCost(const MachineInstr *MI);

(if your target uses the IfConversion.cpp pass)

radar://15077010

llvm-svn: 191671

Enable building the LTO library (.lib and.dll) and llvm-lto.exe on Windows with
MSVC and Mingw as well as re-enabling the associated test.

Patch by Greg Bedwell!

llvm-svn: 191670

clang-apply-replacements unittest Makefile wasn't linking in TransformUtils.

llvm-svn: 191669

when it was actually a Constant*.

There are quite a few other casts to Instruction that might have the same problem,
but this is the only one I have a test case for.

llvm-svn: 191668

The tool now supports a collection of arguments to turn on and provide settings
for the formatting of code affected by applying replacements:
* --format turns on formatting (default style is LLVM)
* --style controls code style settings
* --style-config allows one to explicitly indicate where a style config file
  lives.

The libclangApplyReplacements interface has a new function to turn Replacements
into Ranges to be used with tooling::reformat().

llvm-svn: 191667

The help text for clang-format's -style option and the function that processes
its value is moved to libFormat in this patch. The goal is to enable other
tools that use libFormat and also have a -style option to behave consistently
with clang-format.

llvm-svn: 191666

TemplateDeclInstantiator takes the MultiLevelArgumentList by const-ref
and stores a const-ref member. Thus, we must not pass a temporary
into the constructor.

llvm-svn: 191665

llvm-svn: 191664

For some reason, adding definitions for these load and store
instructions changed whether some of the build bots matched
comparisons as signed or unsigned.

llvm-svn: 191663

llvm-svn: 191662

llvm-svn: 191661

The only thing this does on its own is make the definitions of RISB[HL]G
a bit more precise.  Those instructions are only used by the MC layer at
the moment, so no behavioral change is intended.  The class is needed by
later patches though.

llvm-svn: 191660

Use subreg_hNN and subreg_lNN for the high and low NN bits of a register.
List the low registers first, so that subreg_l32 also means the low 32
bits of a 128-bit register.

Floats are stored in the upper 32 bits of a 64-bit register, so they
should use subreg_h32 rather than subreg_l32.

No behavioral change intended.

llvm-svn: 191659

It now points to the equivalent page on imgtec.com

llvm-svn: 191658

Otherwise if libcxx is built as an LLVM external project (after r191624),
"include(config-ix)" will include config-ix.cmake from LLVM, not from libcxx,
which will result in misconfigured build tree.

llvm-svn: 191657

llvm-svn: 191656

I'm about to add support for high-word operations, so it seemed better
for the low-word registers to have names like R0L rather than R0W.
No behavioral change intended.

llvm-svn: 191655

Previously, comments, could totally confuse it.

Before:
  return
             // true if code is one of a or b.
             code == a ||
         code == b;

After:
  return
      // true if code is one of a or b.
      code == a || code == b;

llvm-svn: 191654

such option I've been able to find in the wild in our build system.

Note that I haven't added test cases for this. I can do so if folks
want, but they're *really* boring considering that this is all generated
code to parse and ignore unsued options.

llvm-svn: 191653

Filter out repeated sections from the X86 disassembler modRMTable. Saves about ~43K from a released build. Unfortunately the disassembler tables are still upwards of 800K.

llvm-svn: 191652

prefix. Sort the ignored boolean 'f' flags at the bottom of this file.
No functionality changed.

llvm-svn: 191651

Add a few more FMA4 disassembler test cases to match the scalar set with regards to combinations of L and W-bits.

llvm-svn: 191650

Add VEX_LIG to scalar FMA4 instructions.
Use VEX_LIG in some of the inheriting checks in disassembler table generator.
Make use of VEX_L_W, VEX_L_W_XS, VEX_L_W_XD contexts.
Don't let VEX_L_W, VEX_L_W_XS, VEX_L_W_XD, VEX_L_W_OPSIZE inherit from their non-L forms unless VEX_LIG is set.
Let VEX_L_W, VEX_L_W_XS, VEX_L_W_XD, VEX_L_W_OPSIZE inherit from all of their non-L or non-W cases.
Increase ranking on VEX_L_W, VEX_L_W_XS, VEX_L_W_XD, VEX_L_W_OPSIZE so they get chosen over non-L/non-W forms.

llvm-svn: 191649