- Jan 05, 2009
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Dan Gohman authored
llvm-svn: 61715
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Devang Patel authored
squash warnings. llvm-svn: 61707
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Evan Cheng authored
llvm-svn: 61686
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Scott Michel authored
- Teach SPU64InstrInfo.td about the remaining signed comparisons, update tests accordingly. llvm-svn: 61672
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Scott Michel authored
- Fix (brcond (setq ...)) bug, where BRNZ should have been used vice BRZ. - Kill unused/unnecessary nodes in SPUNodes.td - Beef out the i64operations.c test harness to use a lot of unaligned loads, test loops and LLVM loop/basic block optimizations; run the test harness successfully on real Cell hardware. llvm-svn: 61664
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- Jan 03, 2009
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Evan Cheng authored
llvm-svn: 61603
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Evan Cheng authored
llvm-svn: 61602
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Scott Michel authored
- Remove custom lowering for BRCOND - Add remaining functionality for branches in SPUInstrInfo, such as branch condition reversal and load/store folding. Updated BrCond test to reflect branch reversal. llvm-svn: 61597
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- Jan 02, 2009
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Scott Michel authored
register copies a little easier to pick out from the output. - Fix bug 3192. llvm-svn: 61591
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Evan Cheng authored
Do not isel load folding bt instructions for pentium m, core, core2, and AMD processors. These are significantly slower than a load followed by a bt of a register. llvm-svn: 61557
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Evan Cheng authored
llvm-svn: 61556
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Evan Cheng authored
Use movaps / movd to extract vector element 0 even with sse4.1. It's still cheaper than pextrw especially if the value is in memory. llvm-svn: 61555
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- Jan 01, 2009
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Duncan Sands authored
promote from i1 all the way up to the canonical SetCC type. In order to discover an appropriate type to use, pass MVT::Other to getSetCCResultType. In order to be able to do this, change getSetCCResultType to take a type as an argument, not a value (this is also more logical). llvm-svn: 61542
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- Dec 31, 2008
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Chris Lattner authored
llvm-svn: 61513
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Scott Michel authored
instruction sequence and cannot ordinarily be simplified by DAGcombine into the various target description files or SPUDAGToDAGISel.cpp. This makes some 64-bit operations legal. - Eliminate target-dependent ISD enums. - Update tests. llvm-svn: 61508
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- Dec 29, 2008
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Bill Wendling authored
Darwin doesn't. Make this optional for platforms. llvm-svn: 61484
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Misha Brukman authored
llvm-svn: 61477
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Scott Michel authored
- Move v4i32, i32 mul into SPUInstrInfo.td, with a few more instruction cleanups there as well. - Make SMUL_LOHI, UMUL_LOHI competely illegal for Cell SPU, to better assist Chris to see the problem in bug 3101. llvm-svn: 61464
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- Dec 27, 2008
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Scott Michel authored
DAGcombine's ability to find reasons to remove truncates when they were not needed. Consequently, the CellSPU backend would produce correct, but _really slow and horrible_, code. Replaced with instruction sequences that do the equivalent truncation in SPUInstrInfo.td. - Re-examine how unaligned loads and stores work. Generated unaligned load code has been tested on the CellSPU hardware; see the i32operations.c and i64operations.c in CodeGen/CellSPU/useful-harnesses. (While they may be toy test code, it does prove that some real world code does compile correctly.) - Fix truncating stores in bug 3193 (note: unpack_df.ll will still make llc fault because i64 ult is not yet implemented.) - Added i64 eq and neq for setcc and select/setcc; started new instruction information file for them in SPU64InstrInfo.td. Additional i64 operations should be added to this file and not to SPUInstrInfo.td. llvm-svn: 61447
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- Dec 25, 2008
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Chris Lattner authored
llvm-svn: 61426
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Chris Lattner authored
llvm-svn: 61425
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Chris Lattner authored
llvm-svn: 61424
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Chris Lattner authored
llvm-svn: 61423
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- Dec 24, 2008
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Bill Wendling authored
llvm-svn: 61420
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Bill Wendling authored
about other platforms. llvm-svn: 61415
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Dan Gohman authored
a symbolic constant. This is unlikely to be intentional, but it shouldn't crash the compiler. llvm-svn: 61408
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Chris Lattner authored
llvm-svn: 61407
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Chris Lattner authored
llvm-svn: 61404
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- Dec 23, 2008
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Dan Gohman authored
llvm-svn: 61400
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Devang Patel authored
llvm-svn: 61392
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Dan Gohman authored
This removes all the _8, _16, _32, and _64 opcodes and replaces each group with an unsuffixed opcode. The MemoryVT field of the AtomicSDNode is now used to carry the size information. In tablegen, the size-specific opcodes are replaced by size-independent opcodes that utilize the ability to compose them with predicates. This shrinks the per-opcode tables and makes the code that handles atomics much more concise. llvm-svn: 61389
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Chris Lattner authored
llvm-svn: 61385
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Mon P Wang authored
Fixed lowering of v8i16 shuffles for v8i16 when we fall back to extract/insert. llvm-svn: 61365
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Dan Gohman authored
llvm-svn: 61356
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- Dec 20, 2008
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Dan Gohman authored
constant shift count that doesn't fit in the shift instruction's immediate field. This fixes PR3242. llvm-svn: 61281
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- Dec 19, 2008
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Dan Gohman authored
that have i32 immediates so that they get selected first. This currently only matters in the JIT, as assemblers will automatically use the smallest encoding. llvm-svn: 61250
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Chris Lattner authored
llvm-svn: 61244
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Rafael Espindola authored
The EH_frame and .eh symbols are now private, except for darwin9 and earlier. The patch also fixes the definition of PrivateGlobalPrefix on pcc linux. llvm-svn: 61242
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- Dec 18, 2008
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Dan Gohman authored
used, mark the defs as dead. llvm-svn: 61215
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Dan Gohman authored
non-entry blocks, so that it doesn't appear use-before-def anywhere. llvm-svn: 61214
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