- May 11, 2012
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Chad Rosier authored
retval. Hoists check before emitting the call to avoid unnecessary work. rdar://11430407 PR12796 llvm-svn: 156628
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Jim Ingham authored
rdar://problem/11419156 llvm-svn: 156627
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Greg Clayton authored
Fixed an issue in the platform options where if no architecture was specified where the platform would fail to select itself with something like: (lldb) platfrom select remote-ios llvm-svn: 156626
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Nuno Lopes authored
llvm-svn: 156625
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Jim Ingham authored
llvm-svn: 156624
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Chad Rosier authored
to selection DAG isel if we're unable to handle a non-double multi-reg retval. rdar://11430407 PR12796 llvm-svn: 156622
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Chad Rosier authored
llvm-svn: 156621
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Manman Ren authored
llvm-svn: 156620
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Kostya Serebryany authored
llvm-svn: 156617
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Kostya Serebryany authored
llvm-svn: 156616
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Preston Gurd authored
llvm-svn: 156615
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Kostya Serebryany authored
llvm-svn: 156614
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Stepan Dyatkovskiy authored
llvm-svn: 156613
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Hans Wennborg authored
llvm-svn: 156612
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Hans Wennborg authored
This fixes a TODO from 2007 :) Previously, LLVM would emit the wrong code here (see the update to test/CodeGen/X86/tls-pie.ll). llvm-svn: 156611
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Silviu Baranga authored
Added the missing bit definition for the 4th bit of the STR (post reg) instruction. It is now set to 0. The patch also sets the unpredictable mask for SEL and SXTB-type instructions. llvm-svn: 156609
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Silviu Baranga authored
Fixed the LLVM ARM v7 assembler and instruction printer for 8-bit immediate offset addressing. The assembler and instruction printer were not properly handeling the #-0 immediate. llvm-svn: 156608
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Richard Smith authored
which expects exactly one argument, include the name of the argument in the diagnostic text. Patch by Terry Long! llvm-svn: 156607
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Rafael Espindola authored
llvm-svn: 156606
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Greg Clayton authored
llvm-svn: 156605
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Argyrios Kyrtzidis authored
Add a test case for going through typedefs until we reach "BOOL", that NSAPI::isObjCTypedef() is doing. llvm-svn: 156604
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Akira Hatanaka authored
llvm-svn: 156603
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Jim Grosbach authored
llvm-svn: 156602
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Jim Grosbach authored
llvm-svn: 156601
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Eli Friedman authored
llvm-svn: 156600
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Manman Ren authored
This patch will optimize the following cases: sub r1, r3 | sub r1, imm cmp r3, r1 or cmp r1, r3 | cmp r1, imm bge L1 TO subs r1, r3 bge L1 or ble L1 If the branch instruction can use flag from "sub", then we can replace "sub" with "subs" and eliminate the "cmp" instruction. rdar: 10734411 llvm-svn: 156599
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Rafael Espindola authored
llvm-svn: 156597
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Greg Clayton authored
Modified the symbolication.Image object to store its uuid as a uuid.UUID object and made an accessor for getting a normalized UUID value out of the image object. Modified the crashlog darwin module to always create a uuid.UUID object when making the symbolication.Image objects. Also modified it to handle some more types of crash log files and improved the register reading for thread registers of crashed threads. llvm-svn: 156596
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Greg Clayton authored
Don't intercept the quit command and override what is was doing. This was causing the "lldb" command line to deadlock when the quit command was executed sometimes. llvm-svn: 156595
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Dan Gohman authored
but it generates int3 on x86 instead of ud2. llvm-svn: 156593
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Eric Christopher authored
compilers and expected defaults. Part of rdar://11325849 llvm-svn: 156592
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Eric Christopher authored
to user only read/write. Part of rdar://11325849 llvm-svn: 156591
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Chad Rosier authored
llvm-svn: 156589
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Greg Clayton authored
"--stack-history" now works if you have MallocStackLogggingNoCompact defined in your app's environment. llvm-svn: 156588
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Jakob Stoklund Olesen authored
The sub-registers explicitly listed in SubRegs in the .td files form a tree. In a complicated register bank, it is possible to have sub-register relationships across sub-trees. For example, the ARM NEON double vector Q0_Q1 is a tree: Q0_Q1 = [Q0, Q1], Q0 = [D0, D1], Q1 = [D2, D3] But we also define the DPair register D1_D2 = [D1, D2] which is fully contained in Q0_Q1. This patch teaches TableGen to find such sub-register relationships, and assign sub-register indices to them. In the example, TableGen will create a dsub_1_dsub_2 sub-register index, and add D1_D2 as a sub-register of Q0_Q1. This will eventually enable the coalescer to handle copies of skewed sub-registers. llvm-svn: 156587
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Greg Clayton authored
llvm-svn: 156586
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Nuno Lopes authored
add an additional parameter to InstCombiner::EmitGEPOffset() to force it to *not* emit operations with NUW flag llvm-svn: 156585
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Greg Clayton authored
Added the ability to get the stack history for a malloc block. This is a work in progress. Checking this in so I can work on it some more. llvm-svn: 156584
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Argyrios Kyrtzidis authored
numberWithBool:/numberWithInteger:/numberWithUnsignedInteger: NSNumber selectors. rdar://11428703 llvm-svn: 156583
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Ted Kremenek authored
llvm-svn: 156582
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