llvm-svn: 36483

llvm-svn: 36473

llvm-svn: 36458

llvm-svn: 36452

Change UsedPhysRegs from array bool to BitVector to save some space. Setting / getting its states now go through MachineFunction.

llvm-svn: 36451

llvm-svn: 36449

llvm-svn: 36447

llvm-svn: 36445

will follow.

llvm-svn: 36435

- A register def / use now implicitly affects sub-register liveness but does
not affect liveness information of super-registers.
- Def of a larger register (if followed by a use later) is treated as
read/mod/write of a smaller register.

llvm-svn: 36434

llvm-svn: 36431

llvm-svn: 36425

llvm-svn: 36422

llvm-svn: 36420

This fixes CodeGen/X86/2007-04-24-VectorCrash.ll

llvm-svn: 36413

real vector type in this case.

llvm-svn: 36402

tests always being true in the process.

llvm-svn: 36387

llvm-svn: 36383

llvm-svn: 36368

llvm-svn: 36356

llvm-svn: 36318

llvm-svn: 36309

add support for alignment attributes on load/store instructions

llvm-svn: 36301

llvm-svn: 36290

X86 32 bits.

llvm-svn: 36283

llvm-svn: 36250

llvm-svn: 36245

single-use nodes, they will be dead soon.  Make sure to remove them before
processing other nodes.  This implements CodeGen/X86/shl_elim.ll

llvm-svn: 36244

llvm-svn: 36242

llvm-svn: 36240

llvm-svn: 36233

wrong operand.

llvm-svn: 36223

This compiles:
int baz(long long a) { return (short)(((int)(a >>24)) >> 9); }

into:
_baz:
        srwi r2, r3, 1
        extsh r3, r2
        blr

on PPC, instead of:
_baz:
        slwi r2, r3, 8
        srwi r2, r2, 9
        extsh r3, r2
        blr

GCC produces:
_baz:
        srwi r10,r4,24
        insrwi r10,r3,24,0
        srawi r9,r3,24
        srawi r3,r10,9
        extsh r3,r3
        blr

This implements CodeGen/PowerPC/shl_elim.ll

llvm-svn: 36221

long live interval that has low usage density.
1. Change order of coalescing to join physical registers with virtual
   registers first before virtual register intervals become too long.
2. Check size and usage density to determine if it's worthwhile to join.
3. If joining is aborted, assign virtual register live interval allocation
   preference field to the physical register.
4. Register allocator should try to allocate to the preferred register
   first (if available) to create identify moves that can be eliminated.

llvm-svn: 36218

llvm-svn: 36216

llvm-svn: 36214

a chance to hack on it.  This compiles:

int baz(long long a) { return (short)(((int)(a >>24)) >> 9); }

into:
_baz:
        slwi r2, r3, 8
        srwi r2, r2, 9
        extsh r3, r2
        blr

instead of:

_baz:
        srwi r2, r4, 24
        rlwimi r2, r3, 8, 0, 23
        srwi r2, r2, 9
        extsh r3, r2
        blr

This implements CodeGen/PowerPC/sign_ext_inreg1.ll

llvm-svn: 36212

llvm-svn: 36180

target for tabs checking.

llvm-svn: 36146

some reason.  :(  Will investigate.

llvm-svn: 36011