CPU, and feature string. Parsing some asm directives can change
subtarget state (e.g. .code 16) and it must be reflected in other
modules (e.g. MCCodeEmitter). That is, the MCSubtargetInfo instance
must be shared.

llvm-svn: 134795

Really force on 64bit for 64-bit targets.  Should fix remaining failures on unknown x86/non-x86 targets.

llvm-svn: 134773

Revert earlier unnecessary hack.  Make sure we correctly force on 64bit and cmov for 64-bit targets.

llvm-svn: 134768

llvm-svn: 134764

llvm-svn: 134760

llvm-svn: 134758

llvm-svn: 134757

llvm-svn: 134755

Default 64-bit target features and SSE2 on when a triple specifies x86-64.  Clean up all the other hacks which are now unnecessary.

llvm-svn: 134753

The normal tBX instruction is predicable, so there's no reason the
pseudos for using it as a return shouldn't be. Gives us some nice code-gen
improvements as can be seen by the test changes. In particular, several
tests now have to disable if-conversion because it works too well and defeats
the test.

llvm-svn: 134746

http://llvm.org/bugs/show_bug.cgi?id=10305

llvm-svn: 134744

is to use this for architectures that have a native FMA instruction.

llvm-svn: 134742

llvm-svn: 134741

llvm-svn: 134739

Found by valgrind.

llvm-svn: 134738

No functional change.

llvm-svn: 134737

llvm-svn: 134734

llvm-svn: 134732

llvm-svn: 134730

llvm-svn: 134729

Fix a FIXME.

llvm-svn: 134727

llvm-svn: 134721

llvm-svn: 134719

No functional change.

llvm-svn: 134714

TableGen'erated MC lowering pseudo-expansion.

llvm-svn: 134712

llvm-svn: 134707

Hook up the TableGen lowering for simple pseudo instructions for ARM and
use it for a subset of the many pseudos the backend has as proof of concept.

More conversions to come.

llvm-svn: 134705

- Each target asm parser now creates its own MCSubtatgetInfo (if needed).
- Changed AssemblerPredicate to take subtarget features which tablegen uses
  to generate asm matcher subtarget feature queries. e.g.
  "ModeThumb,FeatureThumb2" is translated to
  "(Bits & ModeThumb) != 0 && (Bits & FeatureThumb2) != 0".

llvm-svn: 134678

llvm-svn: 134671

llvm-svn: 134668

Fixes PR9602!

llvm-svn: 134665

processor supports it just fine.

Fixes PR9675 and rdar://9740801

llvm-svn: 134664

llvm-svn: 134661

Part of PR10299 and rdar://9740322

llvm-svn: 134653

Fixes PR10149 and rdar://9738585

llvm-svn: 134648

llvm-svn: 134645

llvm-svn: 134641

llvm-svn: 134640

based on a modifier, split it into two functions.

llvm-svn: 134637

llvm-svn: 134633