llvm-svn: 26806

llvm-svn: 26805

scale component of the target addressing mode.

llvm-svn: 26802

5 instructions away.

llvm-svn: 26801

llvm-svn: 26800

llvm-svn: 26795

llvm-svn: 26793

llvm-svn: 26776

llvm-svn: 26758

llvm-svn: 26743

llvm-svn: 26742

registers, and update it on entry to each function, then restore it on exit.

This compiles:

void func(vfloat *a, vfloat *b, vfloat *c) {
        *a = *b * *c + *c;
}

to this:

_func:
        mfspr r2, 256
        oris r6, r2, 49152
        mtspr 256, r6
        lvx v0, 0, r5
        lvx v1, 0, r4
        vmaddfp v0, v1, v0, v0
        stvx v0, 0, r3
        mtspr 256, r2
        blr

GCC produces this (which has additional stack accesses):

_func:
        mfspr r0,256
        stw r0,-4(r1)
        oris r0,r0,0xc000
        mtspr 256,r0
        lvx v0,0,r5
        lvx v1,0,r4
        lwz r12,-4(r1)
        vmaddfp v0,v0,v1,v0
        stvx v0,0,r3
        mtspr 256,r12
        blr

llvm-svn: 26733

llvm-svn: 26722

llvm-svn: 26721

llvm-svn: 26720

1. Use flags on the instructions in the .td file to indicate the PPC970 unit
   type instead of a table in the .cpp file.  Much cleaner.
2. Change the hazard recognizer to build d-groups according to the actual
   algorithm used, not my flawed understanding of it.
3. Model "must be in the first slot" and "must be the only instr in a group"
   accurately.

llvm-svn: 26719

llvm-svn: 26710

llvm-svn: 26697

llvm-svn: 26608

llvm-svn: 26605

asm printer.

llvm-svn: 26599

llvm-svn: 26595

llvm-svn: 26594

llvm-svn: 26591

a nop into Freebench/neural, which speeds it up from 136->129s (~5.4%).

llvm-svn: 26590

llvm-svn: 26588

flushes

llvm-svn: 26587

llvm-svn: 26585

llvm-svn: 26562

implement copysign as a native op if they have it.

llvm-svn: 26541

llvm-svn: 26450

llvm-svn: 26448

void foo(float a, int *b) { *b = a; }

to this:

_foo:
        fctiwz f0, f1
        stfiwx f0, 0, r4
        blr

instead of this:

_foo:
        fctiwz f0, f1
        stfd f0, -8(r1)
        lwz r2, -4(r1)
        stw r2, 0(r4)
        blr

This implements CodeGen/PowerPC/stfiwx.ll, and also incidentally does the
right thing for GCC bugzilla 26505.

llvm-svn: 26447

llvm-svn: 26445

llvm-svn: 26438

but I don't know what other PPC impls do.  If someone could update the proc
table, I would appreciate it :)

llvm-svn: 26421

llvm-svn: 26418

llvm-svn: 26405

inline asms! :)

llvm-svn: 26365

llvm-svn: 26348