careful about crazy methods of capturing pointers using comparisons.
Comparisons of identified objects with null in the default address
space are not captures. And, comparisons of two pointers within the
same identified object are not captures.

llvm-svn: 89421

llvm-svn: 89419

llvm-svn: 89418

llvm-svn: 89417

llvm-svn: 89414

llvm-svn: 89411

llvm-svn: 89410

Patch by Tobias Grosser!

llvm-svn: 89406

llvm-svn: 89404

assembly can confuse things utterly, as it's assumed that instructions in
inline assembly are 4 bytes wide. For Thumb mode, that's often not true,
so the calculations for when alignment padding will be present get thrown off,
ultimately leading to out of range constant pool entry references. Making
more conservative assumptions that padding may be necessary when inline asm
is present avoids this situation.

llvm-svn: 89403

if it is not ultimately captured. Teach BasicAliasAnalysis that a 
local object address which does not escape and is never stored does
not alias with a value resulting from a load.

llvm-svn: 89398

llvm-svn: 89396

llvm-svn: 89389

fixes PR5395.

llvm-svn: 89385

critical edges in PHIElimination.

This has a huge impact on regalloc performance, and we recover almost all of
the 10% compile time regression that edge splitting introduced.

llvm-svn: 89381

$ svn merge -c -89279 https://llvm.org/svn/llvm-project/llvm/trunk
--- Reverse-merging r89279 into '.':
U    lib/CodeGen/AsmPrinter/DwarfException.cpp
U    lib/Target/TargetLoweringObjectFile.cpp
$ svn merge -c -89270 https://llvm.org/svn/llvm-project/llvm/trunk
--- Reverse-merging r89270 into '.':
G    lib/CodeGen/AsmPrinter/DwarfException.cpp
G    lib/Target/TargetLoweringObjectFile.cpp

llvm-svn: 89379

fully specified at this level.  Subclasses of NLdStLN can specify selective
bit(s) for Inst{7-4}, as is done for VLD[234]LN* and VST[234]LN* inside
ARMInstrNEON.td.

llvm-svn: 89377

Fix a small bug.

Fix one case we missed to make sure we reserve registers from
allocation.

llvm-svn: 89376

they are lowered to instruction sequences more complex than a simple
load, such that CodeGen cannot rematerialize them, a reload from a
spill slot is likely to be cheaper than the complex sequence.

llvm-svn: 89374

llvm-svn: 89372

llvm-svn: 89369

everything else.

llvm-svn: 89368

llvm-svn: 89364

llvm-svn: 89363

llvm-svn: 89360

llvm-svn: 89359

llvm-svn: 89357

Add support for spreading register allocation.

Add a -linearscan-skip-count argument (default to 0) that tells the
allocator to remember the last N registers it allocated and skip them
when looking for a register candidate.  This tends to spread out
register usage and free up post-allocation scheduling at the cost of
slightly more register pressure.  The primary benefit is the ability
to backschedule reloads.

This is turned off by default.

llvm-svn: 89356

llvm-svn: 89354

4.2.4, 4.3.4, 4.4.2.
The workaround is to use a local min/max implementation that takes an integer
param, and not a reference to integer param (like std::min does).

llvm-svn: 89352

llvm-svn: 89341

llvm-svn: 89339

llvm-svn: 89337

llvm-svn: 89329

llvm-svn: 89328

llvm-svn: 89326

llvm-svn: 89325

- Support mips1 like load/store of doubles:

Instead of:
  sdc $f0, X($3)
Generate:
  swc $f0, X($3)
  swc $f1, X+4($3)

llvm-svn: 89322

llvm-svn: 89316

All spiller calls in RegAllocLinearScan now go through the new Spiller interface.
The "-new-spill-framework" command line option has been removed. To use the trivial in-place spiller you should now pass "-spiller=trivial -rewriter=trivial".
(Note the trivial spiller/rewriter are only meant to serve as examples of the new in-place modification work. Enabling them will yield terrible, though hopefully functional, code).

llvm-svn: 89311