Commits · 9166ce86e83900d2671b66707461d05e7bf9739a · Roger Ferrer / llvm-epi-0.8 · GitLab

This project is archived. Its data is read-only.

Jul 28, 2017
- AMDGPU: Annotate implicitarg.ptr usage · 9166ce86
  Matt Arsenault authored Jul 28, 2017
  9166ce86
- [AArch64] Standardize suffixes for LSE Atomics mnemonics (NFCI) · 08e88e8d
  Joel Jones authored Jul 28, 2017
  08e88e8d
- [ARM] Add the option to directly access TLS pointer · 25e9e1b8
  Strahinja Petrovic authored Jul 28, 2017
  25e9e1b8
- [MachineOutliner] NFC: Split up getOutliningBenefit · 809d708b
  Jessica Paquette authored Jul 28, 2017
  809d708b
- ARMFrameLowering: Only set ExtraCSSpill for actually unused registers. · c618a466
  Matthias Braun authored Jul 28, 2017
  c618a466
- [X86] Fix latent bug in sibcall eligibility logic · 07a5d437
  Reid Kleckner authored Jul 28, 2017
  07a5d437
- Remove unused function from AArch64 backend (NFC) · 8f4b353e
  Adrian Prantl authored Jul 27, 2017
  8f4b353e
Jul 27, 2017
- [X86] Don't lie about legality to TLI's demanded bits. · c8909937
  Ahmed Bougacha authored Jul 27, 2017
  c8909937
- [AArch64] Remove outdated comment. NFC. · 52cecb1f
  Ahmed Bougacha authored Jul 27, 2017
  52cecb1f
- [AArch64] Fix legality info passed to demanded bits for TBI opt. · 87807c5a
  Ahmed Bougacha authored Jul 27, 2017
  87807c5a
- [ARM] Add use-misched feature, to enable the MachineScheduler. · e3583bdf
  Florian Hahn authored Jul 27, 2017
  e3583bdf
- [X86] SET0 to use XMM registers where possible PR26018 PR32862 · aead31a3
  Dinar Temirbulatov authored Jul 27, 2017
  aead31a3
- [TargetParser] Use enum classes for various ARM kind enums. · 67ddd1d0
  Florian Hahn authored Jul 27, 2017
  67ddd1d0
- [ARM] Mark labels in skipAlignedDPRCS2Spills as fallthrough (NFC). · db479524
  Florian Hahn authored Jul 27, 2017
  db479524
- Added cost of ZEROALL and ZEROUPPER instrs in btver2 cpu. · e255526d
  Andrew V. Tischenko authored Jul 27, 2017
  e255526d
- Re-commit: r309094 [globalisel][tablegen] Fuse the generated tables together. · 8e82af2b
  Daniel Sanders authored Jul 27, 2017
  8e82af2b
- [X86] Tidyup MaskedLoad/Store mask creation. NFCI. · afc1ac27
  Simon Pilgrim authored Jul 27, 2017
  afc1ac27
- [PowerPC] enable optimizeCompareInstr for branch with static branch hint · 967dc58a
  Hiroshi Inoue authored Jul 27, 2017
  967dc58a
- [Hexagon] Fix expensive checks build bot broken in r309230. · 569932d1
  Eugene Zelenko authored Jul 26, 2017
  569932d1
- [Hexagon] Partially revert r309230 which caused some build bots failures. · efd3d588
  Eugene Zelenko authored Jul 26, 2017
  efd3d588
- [Hexagon] Fix some Clang-tidy modernize-use-using and Include What You Use... · e4fc6ee7
  Eugene Zelenko authored Jul 26, 2017
  e4fc6ee7
Jul 26, 2017
- [AMDGPU] Optimize SI_IF lowering for simple if regions · 3197eb69
  Stanislav Mekhanoshin authored Jul 26, 2017
  3197eb69
- [ARM] Minor cosmetic edits (NFC) · b3ed4bcb
  Evandro Menezes authored Jul 26, 2017
  b3ed4bcb
- [AArch64] Adjust the cost model for Exynos M1 and M2 · d192a8ae
  Evandro Menezes authored Jul 26, 2017
  d192a8ae
- AMDGPU : Widen extending scalar loads to 32-bits. · a126a13b
  Wei Ding authored Jul 26, 2017
  a126a13b
- AMDGPU: Fix using SMRD instructions for argument loads in functions · 894e53d6
  Matt Arsenault authored Jul 26, 2017
  894e53d6
- AMDGPU/GlobalISel: Mark 32-bit G_OR as legal · 55038cd1
  Tom Stellard authored Jul 26, 2017
  55038cd1
- Change CallLoweringInfo::CS to be an ImmutableCallSite instead of a pointer. NFCI. · 081ffe2f
  Peter Collingbourne authored Jul 26, 2017
  081ffe2f
- Simplify. NFC. · e06e4df8
  Rafael Espindola authored Jul 26, 2017
  e06e4df8
- [Hexagon] Mark raise_relocation_error as NORETURN. · 239e4b93
  Florian Hahn authored Jul 26, 2017
  239e4b93
- [NFC] test commit. · df0ee9e1
  Stefan Pintilie authored Jul 26, 2017
  df0ee9e1
- DAGCombiner: Extend reduceBuildVecToTrunc to handle non-zero offset · 092f1991
  Zvi Rackover authored Jul 26, 2017
  092f1991
- [COFF, ARM64] Fix symbol offsets in ADRP/ADD/LDR/STR relocations · 0b7bf7a2
  Martin Storsjo authored Jul 26, 2017
  0b7bf7a2
- [ARM] GlobalISel: Map G_GLOBAL_VALUE to GPR · a5d6518e
  Diana Picus authored Jul 26, 2017
  a5d6518e
- [ARM] GlobalISel: Mark G_GLOBAL_VALUE as legal · b1fd7849
  Diana Picus authored Jul 26, 2017
  b1fd7849
- [X86][LLVM]Expanding Supports lowerInterleavedStore() in X86InterleavedAccess. · c1918ad5
  Michael Zuckerman authored Jul 26, 2017
  c1918ad5
- TargetLowering: Change isShuffleMaskLegal's mask argument type to ArrayRef<int>. NFCI. · 1b736822
  Zvi Rackover authored Jul 26, 2017
  1b736822
- [X86][LLVM]Expanding Supports lowerInterleavedStore() in X86InterleavedAccess part1. · 60bc7e0f
  Michael Zuckerman authored Jul 26, 2017
  60bc7e0f
- [X86] Prevent selecting masked aligned load instructions if the load should be non-temporal · 050c9c8f
  Craig Topper authored Jul 26, 2017
  050c9c8f
- [AArch64] Fix some Clang-tidy modernize-use-using and Include What You Use... · 96d933da
  Eugene Zelenko authored Jul 25, 2017
  96d933da