to a vector that CGT stores instead of synthesizing it on every 
call.

llvm-svn: 98910

llvm-svn: 98908

llvm-svn: 98906

llvm-svn: 98904

llvm-svn: 98900

like this:

 def : Pat<(add ...),
           (FOOINST)>;

When fooinst only has a single implicit def (e.g. to R1).  This will be handled
as if written as (set R1, (FOOINST ...))

llvm-svn: 98897

llvm-svn: 98879

shouldn't change this.

llvm-svn: 98872

llvm-svn: 98871

llvm-svn: 98870

instruction.  Instructions must use 'ins' and 'outs' now.

llvm-svn: 98868

Add checking that the input/output operand list in spelled right.

llvm-svn: 98865

to allow custom post-processing of matched instructions.

llvm-svn: 98857

llvm-svn: 98820

U    test/CodeGen/ARM/tls2.ll
U    test/CodeGen/ARM/arm-negative-stride.ll
U    test/CodeGen/ARM/2009-10-30.ll
U    test/CodeGen/ARM/globals.ll
U    test/CodeGen/ARM/str_pre-2.ll
U    test/CodeGen/ARM/ldrd.ll
U    test/CodeGen/ARM/2009-10-27-double-align.ll
U    test/CodeGen/Thumb2/thumb2-strb.ll
U    test/CodeGen/Thumb2/ldr-str-imm12.ll
U    test/CodeGen/Thumb2/thumb2-strh.ll
U    test/CodeGen/Thumb2/thumb2-ldr.ll
U    test/CodeGen/Thumb2/thumb2-str_pre.ll
U    test/CodeGen/Thumb2/thumb2-str.ll
U    test/CodeGen/Thumb2/thumb2-ldrh.ll
U    utils/TableGen/TableGen.cpp
U    utils/TableGen/DisassemblerEmitter.cpp
D    utils/TableGen/RISCDisassemblerEmitter.h
D    utils/TableGen/RISCDisassemblerEmitter.cpp
U    Makefile.rules
U    lib/Target/ARM/ARMInstrNEON.td
U    lib/Target/ARM/Makefile
U    lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp
U    lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
U    lib/Target/ARM/AsmPrinter/ARMInstPrinter.h
D    lib/Target/ARM/Disassembler
U    lib/Target/ARM/ARMInstrFormats.td
U    lib/Target/ARM/ARMAddressingModes.h
U    lib/Target/ARM/Thumb2ITBlockPass.cpp

llvm-svn: 98640

(RISCDisassemblerEmitter) which emits the decoder functions for ARM and Thumb,
and the disassembler core which invokes the decoder function and builds up the
MCInst based on the decoded Opcode.

Added sub-formats to the NeonI/NeonXI instructions to further refine the NEONFrm
instructions to help disassembly.

We also changed the output of the addressing modes to omit the '+' from the
assembler syntax #+/-<imm> or +/-<Rm>.  See, for example, A8.6.57/58/60.

And modified test cases to not expect '+' in +reg or #+num.  For example,

; CHECK:       ldr.w	r9, [r7, #28]

llvm-svn: 98637

have enums for them.

llvm-svn: 98597

now enforces that input/output named values have hte same type.

llvm-svn: 98535

changing the primary datastructure from being a 
"std::vector<unsigned char>" to being a new TypeSet class
that actually has (gasp) invariants!

This changes more things than I remember, but one major
innovation here is that it enforces that named input 
values agree in type with their output values.

This also eliminates code that transparently assumes (in 
some cases) that SDNodeXForm input/output types are the
same, because this is wrong in many case.

This also eliminates a bug which caused a lot of ambiguous
patterns to go undetected, where a register class would
sometimes pick the first possible type, causing an
ambiguous pattern to get arbitrary results.

With all the recent target changes, this causes no 
functionality change!

llvm-svn: 98534

llvm-svn: 98468

needs to be majorly refactored, but this spot bugfix allows
things like:

 def vmrghw_shuffle : PatFrag<(ops node:$lhs, node:$rhs),
                             (vector_shuffle (v4i32 node:$lhs), node:$rhs), [{
...

llvm-svn: 97952

llvm-svn: 97912

llvm-svn: 97911

Now it will factor things like this:

CheckType i32
  ...
CheckOpcode ISD::AND
  CheckType i64
  ...

into:

SwitchType:
  i32: ...
  i64:
    CheckOpcode ISD::AND
    ...

This shrinks hte table by a few bytes, nothing spectacular.

llvm-svn: 97908

for CheckValueTypeMatcher.  The isContradictory implementation
helps us factor better, shrinking x86 table from 79144 -> 78896
bytes.

llvm-svn: 97905

As in 'llvmc -O2 -O2 test.c'.

llvm-svn: 97787

we sometimes emit nodes multiple times to string buffers to size them.
Compute the histogram correctly.

llvm-svn: 97708

llvm-svn: 97705

sequence, just emit instruction predicates right before them.  This
exposes yet more factoring opportunitites, shrinking the X86 table 
to 79144 bytes.

llvm-svn: 97704

as the very last thing before node emission.  This should
dramatically reduce the number of times we do 'MatchAddress'
on X86, speeding up compile time.  This also improves comments
in the tables and shrinks the table a bit, now down to 
80506 bytes for x86.

llvm-svn: 97703

numbers a ComplexPat will match into.

llvm-svn: 97696

SwitchOpcodeMatcher) and have DAGISelMatcherOpt form it.  This
speeds up selection, particularly for X86 which has lots of 
variants of instructions with only type differences.

llvm-svn: 97645

to itself, even though this isn't wildly useful.

llvm-svn: 97574

llvm-svn: 97556

stuff now that we don't care about emulating the old broken 
behavior of the old isel.  This eliminates the 
'CheckChainCompatible' check (along with IsChainCompatible) which
did an incorrect and inefficient scan *up* the chain nodes which
happened as the pattern was being formed and does the validation
at the end in HandleMergeInputChains when it forms a structural 
pattern.  This scans "down" the graph, which means that it is
quickly bounded by nodes already selected.  This also handles
token factors that get "trapped" in the dag.

Removing the CheckChainCompatible nodes also shrinks the 
generated tables by about 6K for X86 (down to 83K).

There are two pieces remaining before I can nuke PreprocessRMW:
1. I xfailed a test because we're now producing worse code in a 
   case that has nothing to do with the change: it turns out that
   our use of MorphNodeTo will leave dead nodes in the graph
   which (depending on how the graph is walked) end up causing
   bogus uses of chains and blocking matches.  This is really 
   bad for other reasons, so I'll fix this in a follow-up patch.

2. CheckFoldableChainNode needs to be improved to handle the TF.

llvm-svn: 97539

llvm-svn: 97527

llvm-svn: 97517

now that it is gone.

llvm-svn: 97516

llvm-svn: 97515

EmitMergeInputChainsMatcher node up into EmitResultCode.  This
doesn't have much of an effect on the generated code, the X86
table is exactly the same size.

llvm-svn: 97514