llvm-svn: 47695

llvm-svn: 47687

llvm-svn: 47680

llvm-svn: 47669

Don't track max alignment during stack object allocations since they can be deleted later. Let PEI compute it.

llvm-svn: 47668

llvm-svn: 47663

llvm-svn: 47662

llvm-svn: 47657

ComputeMaskedBits to use the APInt form, and remove the
non-APInt form.

llvm-svn: 47654

llvm-svn: 47653

Change several cases in SimplifyDemandedMask that don't ever do any
simplifying to reuse the logic in ComputeMaskedBits instead of
duplicating it.

llvm-svn: 47648

llvm-svn: 47633

llvm-svn: 47629

llvm-svn: 47628

would have been a Godsend here!

llvm-svn: 47625

first commit of new LTO system.  It is not hooked up in the llvm/tools/Makefile, so no one will build it be default yet

llvm-svn: 47621

llvm-svn: 47619

llvm-svn: 47616

Remove unnecessary getOperand/setOperand overriders.
Simplify getReturnValue()

llvm-svn: 47614

Unify to ReturnInst::init() member functions.

llvm-svn: 47611

llvm-svn: 47607

llvm-svn: 47597

llvm-svn: 47587

llvm-svn: 47577

llvm-svn: 47576

and StoreSDNode into LSBaseSDNode.

llvm-svn: 47570

llvm-svn: 47563

a SignBitIsZero function to simplify a common use case.

llvm-svn: 47561

llvm-svn: 47558

llvm-svn: 47556

llvm-svn: 47555

that combines getValueType and MVT::getSizeInBits, since this
occurrs frequently.

llvm-svn: 47552

llvm-svn: 47545

%r3 on PPC) in their ASM files. However, it's hard for humans to read
during debugging. Adding a new field to the register data that lets you
specify a different name to be printed than the one that goes into the
ASM file -- %x3 instead of %r3, for instance.

llvm-svn: 47534

for CellSPU modifications:

- SPUInstrInfo.td refactoring: "multiclass" really is _your_ friend.
- Other improvements based on refactoring effort in SPUISelLowering.cpp,
  esp. in SPUISelLowering::PerformDAGCombine(), where zero amount shifts and
  rotates are now eliminiated, other scalar-to-vector-to-scalar silliness
  is also eliminated.
- 64-bit operations are being implemented, _muldi3.c gcc runtime now
  compiles and generates the right code. More work still needs to be done.

llvm-svn: 47532

llvm-svn: 47516

llvm-svn: 47511

llvm-svn: 47510

To support multiple return values, now ret instruction supports multiple operands instead of one aggregate operand.

llvm-svn: 47508

stuff into ParamAttrsList.h.  Per feedback from
ParamAttrs changes.

llvm-svn: 47504