Commits · 91b079a9fcc6b889f800f181a2f1abcc81a2c2a5 · Roger Ferrer / llvm-epi-0.8 · GitLab

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Apr 09, 2014
- Cannot have the base class destructor be private (or explicitly deleted); fixing the build bots. · 91b079a9
  Aaron Ballman authored Apr 09, 2014
  91b079a9
- Thread Safety Analysis: some minor cleanups to the latest thread safety... · 3f993c13
  Aaron Ballman authored Apr 09, 2014
  3f993c13
- Revert "Revert "YAMLIO: Encode ambiguous hex strings explicitly"" · 97d8ee38
  David Majnemer authored Apr 09, 2014
  97d8ee38
- Inject unique_ptr/shared_ptr into the test instead of using <memory> · fec969a0
  Samuel Benzaquen authored Apr 09, 2014
  fec969a0
- Use the default TID format in curses UI · 5b031ebc
  Ed Maste authored Apr 09, 2014
  5b031ebc
- obj2yaml: Don't crash if the characteristics field is zero · 3bb60739
  David Majnemer authored Apr 09, 2014
  3bb60739
- Add the offload directory which contains the code needed to support · 33f7b24d
  Jim Cownie authored Apr 09, 2014
  33f7b24d
- [NVPTX] Add preliminary intrinsics and codegen support for textures/surfaces · 30d56a7b
  Justin Holewinski authored Apr 09, 2014
  30d56a7b
- [NVPTX] Add support for addrspacecast in global variable initializers,... · 9d852a8e
  Justin Holewinski authored Apr 09, 2014
  9d852a8e
- [NVPTX] Add query support for read-write images and managed variables · 5959695a
  Justin Holewinski authored Apr 09, 2014
  5959695a
- Do not rely on invalid pthread API use in thread test · 65629832
  Ed Maste authored Apr 09, 2014
  65629832
- Fix some doc and comment typos · 16f98b25
  Alp Toker authored Apr 09, 2014
  16f98b25
- [ARM64] Change SYS without a register to an alias to make disassembling more consistant. · 246b0b61
  Bradley Smith authored Apr 09, 2014
  246b0b61
- [ARM64] Correctly disassemble ISB operand as ISB not DBarrier. · 2cef19a2
  Bradley Smith authored Apr 09, 2014
  2cef19a2
- [ARM64] Properly support both apple and standard syntax for FMOV · 239120ca
  Bradley Smith authored Apr 09, 2014
  239120ca
- [ARM64] Flag setting logical/add/sub immediate instructions don't use SP. · a2308f47
  Bradley Smith authored Apr 09, 2014
  a2308f47
- [ARM64] Conditional branches must always print their condition code, even AL. · f280e918
  Bradley Smith authored Apr 09, 2014
  f280e918
- [ARM64] Fix disassembly logic for extended loads/stores with 32-bit registers. · a19b7e83
  Bradley Smith authored Apr 09, 2014
  a19b7e83
- [ARM64] When printing a pre-indexed address with #0, the ', #0' is not optional. · a0d7a9a1
  Bradley Smith authored Apr 09, 2014
  a0d7a9a1
- [ARM64] Add missing shifted register MVN alias to ORN · 70c6acbb
  Bradley Smith authored Apr 09, 2014
  70c6acbb
- [ARM64] SXTW/UXTW are only valid aliases for 32-bit operations. · 403bbf95
  Bradley Smith authored Apr 09, 2014
  403bbf95
- [ARM64] Fix canonicalisation of MOVs. MOV is too complex to be modelled by a dumb alias. · 779238a2
  Bradley Smith authored Apr 09, 2014
  779238a2
- [ARM64] Fixup ADR/ADRP parsing such that they accept immediates and all labels types · f823079a
  Bradley Smith authored Apr 09, 2014
  f823079a
- [ARM64] Ensure sp is decoded as SP, not XZR in LD1 instructions. · af2710c9
  Bradley Smith authored Apr 09, 2014
  af2710c9
- [ARM64] Tighten up the special casing in emitting arithmetic extends. UXTW... · a0dce246
  Bradley Smith authored Apr 09, 2014
  a0dce246
- [ARM64] Rename LR to the UAL-compliant 'X30'. · 3971d3dc
  Bradley Smith authored Apr 09, 2014
  3971d3dc
- [ARM64] Rename FP to the UAL-compliant 'X29'. · 6f1aa59c
  Bradley Smith authored Apr 09, 2014
  6f1aa59c
- [ARM64] Add a PostEncoderMethod to FCMP - the Rm field should canonically be... · 5511f080
  Bradley Smith authored Apr 09, 2014
  5511f080
- [ARM64] SCVTF and FCVTZS/U are undefined if scale<5> == 0. · eb4ca04d
  Bradley Smith authored Apr 09, 2014
  eb4ca04d
- [ARM64] EXT and EXTR instructions on v8i8 and W regs respectively must have... · db7b9b17
  Bradley Smith authored Apr 09, 2014
  db7b9b17
- [ARM64] Scaled fixed-point FCVTZSs should also have bit 29 set to zero. · 60e76678
  Bradley Smith authored Apr 09, 2014
  60e76678
- [ARM64] UBFM/BFM is undefined on w registers when imms<5> or immr<5> is 1. · 7525b472
  Bradley Smith authored Apr 09, 2014
  7525b472
- [ARM64] Floating point to fixed point scaled conversions are only available on fcvtzs and fcvtzu. · 0243aa33
  Bradley Smith authored Apr 09, 2014
  0243aa33
- [ARM64] Port over the PostEncoderMethod fix for SMULH/UMULH from AArch64. · 8f906a3c
  Bradley Smith authored Apr 09, 2014
  8f906a3c
- [ARM64] Add missing tlbi operands and error for extra/missing register on tlbi aliases. · 9f29b726
  Bradley Smith authored Apr 09, 2014
  9f29b726
- [ARM64] Rework system register parsing to overcome SPSel clash in MSR variants. · e8b4166a
  Bradley Smith authored Apr 09, 2014
  e8b4166a
- [ARM64] Port over the PostEncoderMethod from AArch64 for exclusive loads and... · bc35b1f1
  Bradley Smith authored Apr 09, 2014
  bc35b1f1
- [ARM64] Use PStateMapper to ensure that MSRcpsr operands are validated during disassembly. · 4925be9b
  Bradley Smith authored Apr 09, 2014
  4925be9b
- [ARM64] Remove PrefetchOp and use ARM64PRFM instead. · 3339427e
  Bradley Smith authored Apr 09, 2014
  3339427e
- [ARM64] Add WZR to isGPR32Register, since every use needs to check for this anyway. · 16478c4c
  Bradley Smith authored Apr 09, 2014
  16478c4c