'insertvalue' instructions that recreate the structure returned by the
'landingpad' instruction. Because the 'insertvalue' instruction isn't supported
by FastISel, this can save a bit of time during -O0 compilation.

llvm-svn: 148520

llvm-svn: 148513

llvm-svn: 148495

llvm-svn: 148493

rdar://10531041.

llvm-svn: 148490

llvm-svn: 148489

llvm-svn: 148487

llvm-svn: 148486

llvm-svn: 148485

llvm-svn: 148473

llvm-svn: 148467

llvm-svn: 148466

llvm-svn: 148465

llvm-svn: 148464

llvm-svn: 148462

llvm-svn: 148459

llvm-svn: 148456

llvm-svn: 148455

  to instruction right after the last instruction in the bundle.
- Add a finalizeBundle() variant that doesn't specify LastMI. Instead, the code
  will find the last instruction in the bundle by following the 'InsideBundle'
  marker. This is useful in case bundles are formed early (i.e. during MI
  scheduling) but finalized later (i.e. after register allocator has finished
  rewriting virtual registers with physical registers).

llvm-svn: 148444

llvm-svn: 148442

llvm-svn: 148440

It adds register mask operands to x86 call instructions.  Once all the
backend passes support register mask operands, this will be permanently
enabled.

llvm-svn: 148438

This is similar to implicit register operands.  MC doesn't understand
register liveness and call clobbers.

llvm-svn: 148437

This SelectionDAG node will be attached to call nodes by LowerCall(),
and eventually becomes a MO_RegisterMask MachineOperand on the
MachineInstr representing the call instruction.

LowerCall() will attach a register mask that depends on the calling
convention.

llvm-svn: 148436

llvm-svn: 148434

Explicit pc-relative syntax. For example, "ldrb r2, [pc, #-22]".

rdar://10250964

llvm-svn: 148432

llvm-svn: 148431

llvm-svn: 148427

If the fixup is out of range for the Thumb1 instruction, relax it
to the Thumb2 encoding instead.

rdar://10711829

llvm-svn: 148424

If the two fragments are in the same Atom, then the difference
expression is resolvable at compile time. Previously we were checking
that they were in the same fragment, but that breaks down in the
presence of instruction relaxation which has multiple fragments in the
same atom.

rdar://10711829

llvm-svn: 148423

llvm-svn: 148422

llvm-svn: 148419

of recognizing them by name.

llvm-svn: 148416

llvm-svn: 148415

llvm-svn: 148408

llvm-svn: 148401

llvm-svn: 148400

llvm-svn: 148384

Fix a bug in the type-legalization of vector integers. When we bitcast one vector type to another, we must not bitcast the result if one type is widened while the other is promoted.

llvm-svn: 148383

Fix ISD::REG_SEQUENCE to accept physical registers and change TwoAddressInstructionPass to insert copies for any physical reg operands of the REG_SEQUENCE

llvm-svn: 148377