llvm-svn: 108366

patch by Michael Spencer!

llvm-svn: 108342

in the literal field of an instruction. E.g.,
long long foo(long long a) {
  return a - 734439407618LL;
}

rdar://7038284

llvm-svn: 108339

Patch by Brian Lucas. PR7636.

llvm-svn: 108332

llvm-svn: 108328

address cannot be allocated a register is in 32-bit mode where the first
three arguments are marked inreg. In that case EAX, EDX, and ECX will be
used for argument passing.

This fixes PR7610.

llvm-svn: 108327

llvm-svn: 108324

of the value of the immediate.

llvm-svn: 108323

llvm-svn: 108309

Radar 7373643.

llvm-svn: 108303

constants, since they may not be emited near the other instructions
which get the same line, and this confuses debug info.

llvm-svn: 108302

llvm-svn: 108286

NEON VMOV-immediate instructions.  This simplifies some things.

llvm-svn: 108275

Add the x86 VEX_L form to handle special cases where VEX_L must be set.

llvm-svn: 108274

llvm-svn: 108265

Extend the r107852 optimization which turns some fp compare to code sequence using only i32 operations. It now optimize some f64 compares when fp compare is exceptionally slow (e.g. cortex-a8). It also catches comparison against 0.0.

llvm-svn: 108258

llvm-svn: 108256

llvm-svn: 108254

with this commit the callee moves to the end of
the operand array (from the start) and the call
arguments now start at index 0 (formerly 1)

this ordering is now consistent with InvokeInst

this commit only flips the switch,
functionally it is equivalent to
r101465

I intend to commit several cleanups after a few
days of soak period

llvm-svn: 108240

avoid replicated code.

llvm-svn: 108227

disassembler.  Remove some code from the disassembler to
compensate, unbreaking disassembly of lea's.

llvm-svn: 108226

llvm-svn: 108224

llvm-svn: 108223

llvm-svn: 108222

Move some SIMD fragment code into X86InstrFragmentsSIMD so that the
utility classes can be used from multiple files.  This will aid
transitioning to a new refactored x86 SIMD specification.

llvm-svn: 108213

llvm-svn: 108207

llvm-svn: 108204

SD instructions too, in addition to SS instructions. And
add a comment about it.

llvm-svn: 108191

instructions already have implicit defs of LR.  The comment suggests that
this is intended to fix something like pr6111, but it doesn't really do
that either.

llvm-svn: 108186

llvm-svn: 108184

llvm-svn: 108167

support branching on x87 comparisons yet. This fixes PR7624.

llvm-svn: 108149

llvm-svn: 108130

llvm-svn: 108123

AggressiveAntiDepBreaker should not be using getPhysicalRegisterRegClass. An
instruction might be using a register that can only be replaced with one from
a subclass of getPhysicalRegisterRegClass.

With this patch we use getMinimalPhysRegClass. This is correct, but
conservative. We should check the uses of the register and select the
largest register class that can be used in all of them.

llvm-svn: 108122

This fixes PR7375.

llvm-svn: 108120

getMinimalPhysRegClass. It was used to produce spills, and it is better to
use the most specific class if possible.

Update getLoadStoreRegOpcode to handle GR32_AD.

llvm-svn: 108115

The only folding these load/store architectures can do is converting COPY into a
load or store, and the target independent part of foldMemoryOperand already
knows how to do that.

llvm-svn: 108099

operations in x87 code.

llvm-svn: 108098

llvm-svn: 108097