mostly the same.

llvm-svn: 98402

llvm-svn: 98398

llvm-svn: 98395

llvm-svn: 98394

remove it.

llvm-svn: 98390

instead of Pseudo, which helps Thumb decoder to recognize them as Thumb instr.

llvm-svn: 98285

for the NLP because the object it's pointing to may be internal to the file.

This seems counter-intuitive, but bear with me. When we place the LSDA into the
TEXT section, the type info pointers need to be indirect and pc-rel. We
accomplish this by using NLPs. However, sometimes the types are local to the
file. GCC gets around this by not using a NLP in this case, but a "regular"
indirection like this:

GCC_except_tbl:
  .long Lfoo-.

__ZTIA:  @ This is local
  ...

Lfoo:
  .long __ZTIA

LLVM prefers NLPs on Darwin. In fact, it's more optimal for load performance to
use them.

llvm-svn: 98218

Plus fixed the encoding of t2LDRDpci such that P = 1 and W = 0 (offset mode).

llvm-svn: 98217

llvm-svn: 98215

Radar 7686922.

llvm-svn: 98210

Patch by Sean Callanan.

llvm-svn: 98200

indicates that an MCSymbol is external or not. (It's true if it's external.)
This will be used to specify the correct information to add to non-lazy
pointers. That will be explained further when this bit is used.

llvm-svn: 98199

400.perlbench for the nightly tests.

llvm-svn: 98183

llvm-svn: 98182

operands into their own PrintMethod, in order not to pollute the printOperand()
impl with disassembly only Imm modifiers.

llvm-svn: 98172

llvm-svn: 98124

llvm-svn: 98109

is preparatory to having PEI's scavenged frame index value reuse logic
properly distinguish types of frame values (e.g., whether the value is
stack-pointer relative or frame-pointer relative).

No functionality change.

llvm-svn: 98086

what fields of the CPSR or SPSR are affected.

llvm-svn: 98085

register is involved for thumb1. Work around this for the moment by only
re-using SP-relative offsets. This is temporary 'til the code can distinguish
multiple base registers.

llvm-svn: 98071

Place the LSDA into the TEXT section for ARM platforms. This involves making the
encoding indirect, pcrel, and sdata4 instead of an absolute pointer. The
references to the type infos are then non-lazy pointers. Revision 98019 changed
the encoding of non-lazy pointers to add the symbol to the non-lazy pointer
definition if it's a local symbol (otherwise, it's external and set to '0' so
that the loader can adjust it to the real value). This paved the way for this
change to work on ARM.

llvm-svn: 98068

bear with the awful code. It won't last in its current state beyond tonight.

llvm-svn: 98040

llvm-svn: 98019

llvm-svn: 98018

llvm-svn: 98004

immediate instructions cannot set the condition codes, so they do not have
the extra cc_out operand.  We hit an assertion during tail duplication
because the instruction being duplicated had more operands that expected.

llvm-svn: 98001

example, this:

(set DPR:$dst, (fsub (fneg (fmul DPR:$a, DPR:$b)), DPR:$dstin))

is ambiguous because DPR contains both f64 and v2f32.  tblgen
currently accidentally picks f64 because it's first in the 
regclass.

llvm-svn: 97955

Patch by John Tytgat!

llvm-svn: 97886

registers may be restored via a pop instruction, not just a tRestore.
This fixes nightly test 471.omnetep for Thumb1.

llvm-svn: 97867

llvm-svn: 97776

of either sxtb16 or uxtb16, and the unified syntax does not specify ".w".

llvm-svn: 97760

frame pointer.

llvm-svn: 97755

an undef value.  This is only going to come up for bugpoint-reduced tests --
correct programs will not access memory at undefined addresses -- so it's not
worth the effort of doing anything more aggressive.

llvm-svn: 97745

Instruction (PLI) for disassembly only.

According to A8.6.120 PLI (immediate, literal), for example, different
instructions are generated for "pli [pc, #0]" and "pli [pc, #-0"].  The
disassembler solves it by mapping -0 (negative zero) to -1, -1 to -2, ..., etc.

llvm-svn: 97731

MULS <Rdm>, <Rn>, <Rdm>

according to A8.6.105 MUL Encoding T1.

llvm-svn: 97675

and STRHT for disassembly only.

llvm-svn: 97655

for disassembly only.

llvm-svn: 97632

- Change MachineInstr::isIdenticalTo to take a new option that determines whether it should skip checking defs or at least virtual register defs. This subsumes part of the TargetInstrInfo::isIdentical functionality.
- Eliminate TargetInstrInfo::isIdentical and replace it with produceSameValue. In the default case, produceSameValue just checks whether two machine instructions are identical (except for virtual register defs). But targets may override it to check for unusual cases (e.g. ARM pic loads from constant pools).

llvm-svn: 97628

llvm-svn: 97617

disassembly only.

llvm-svn: 97614