llvm-svn: 27170

llvm-svn: 27168

llvm-svn: 27167

llvm-svn: 27166

llvm-svn: 27160

llvm-svn: 27159

manner that the LowerSwitch LLVM to LLVM pass does: emitting a binary
search tree of basic blocks.  The new approach has several advantages:
it is faster, it generates significantly smaller code in many cases, and
it paves the way for implementing dense switch tables as a jump table by
handling switches directly in the instruction selector.

This functionality is currently only enabled on x86, but should be safe for
every target.  In anticipation of making it the default, the cfg is now
properly updated in the x86, ppc, and sparc select lowering code.

llvm-svn: 27156

llvm-svn: 27153

llvm-svn: 27152

llvm-svn: 27151

llvm-svn: 27150

llvm-svn: 27149

llvm-svn: 27148

non-predicate altivec compare intrinsics.

llvm-svn: 27143

intrinsics.

llvm-svn: 27142

llvm-svn: 27139

llvm-svn: 27136

CodeGen/PowerPC/eqv-andc-orc-nor.ll:VNOR/VANDC

llvm-svn: 27135

llvm-svn: 27132

llvm-svn: 27127

llvm-svn: 27120

series of unpack and interleave ops.

llvm-svn: 27119

llvm-svn: 27118

Add a bunch of patterns for different datatypes, e.g. bit_convert, undef and
zero vector support.

llvm-svn: 27117

llvm-svn: 27116

llvm-svn: 27115

llvm-svn: 27112

llvm-svn: 27109

 <int -1, int -1, int -1, int -1>
and
 <int 65537, int 65537, int 65537, int 65537>

Using things like:
  vspltisb v0, -1
and:
  vspltish v0, 1

instead of using constant pool loads.

This implements CodeGen/PowerPC/vec_splat.ll:splat_imm_i{32|16}.

llvm-svn: 27106

llvm-svn: 27103

llvm-svn: 27102

llvm-svn: 27100

llvm-svn: 27096

llvm-svn: 27095

llvm-svn: 27094

llvm-svn: 27091

llvm-svn: 27088

llvm-svn: 27087

llvm-svn: 27083

llvm-svn: 27081