- Jul 20, 2011
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Evan Cheng authored
There is still a bit more refactoring left to do in Targets. But we are now very close to fixing all the layering issues in MC. llvm-svn: 135611
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- Jul 18, 2011
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Evan Cheng authored
to MCRegisterInfo. Also initialize the mapping at construction time. This patch eliminate TargetRegisterInfo from TargetAsmInfo. It's another step towards fixing the layering violation. llvm-svn: 135424
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Chris Lattner authored
llvm-svn: 135375
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- Jul 16, 2011
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Bruno Cardoso Lopes authored
1) Make non-legal 256-bit loads to be promoted to v4i64. This lets us canonize the loads and handle things the same way we use to handle for 128-bit registers. Despite of what one of the removed comments explained, the load promotion would not mess with VPERM, it's only a matter of doing the appropriate bitcasts when this instructions comes to be introduced. Also make LOAD v8i32 legal. 2) Doing 1) exposed two bugs: - v4i64 was being promoted to itself for several opcodes (introduced in r124447 by David Greene) causing endless recursion and the stack to explode. - there was no support for allOnes BUILD_VECTORs and ANDNP would fail to match because it was generating early target constant pools during lowering. 3) The testcases are already checked-in, doing 1) exposed the bugs in the current testcases. 4) Tidy up code to be more clear and explicit about AVX. llvm-svn: 135313
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- Jul 14, 2011
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Eric Christopher authored
when determining validity of matching constraint. Allow i1 types access to the GR8 reg class for x86. Fixes PR10352 and rdar://9777108 llvm-svn: 135180
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Nadav Rotem authored
[VECTOR-SELECT] During type legalization we often use the SIGN_EXTEND_INREG SDNode. When this SDNode is legalized during the LegalizeVector phase, it is scalarized because non-simple types are automatically marked to be expanded. In this patch we add support for lowering SIGN_EXTEND_INREG manually. This fixes CodeGen/X86/vec_sext.ll when running with the '-promote-elements' flag. llvm-svn: 135144
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- Jul 13, 2011
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Bruno Cardoso Lopes authored
general version of X86ISD::ANDNP also opened the room for a little bit of refactoring. llvm-svn: 135088
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Bruno Cardoso Lopes authored
it's later selected to a ANDNPD/ANDNPS instruction instead of the PANDN instruction. Rename it. llvm-svn: 135087
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- Jul 08, 2011
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Julien Lerouge authored
http://llvm.org/bugs/show_bug.cgi?id=10305 llvm-svn: 134744
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Cameron Zwarich authored
is to use this for architectures that have a native FMA instruction. llvm-svn: 134742
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Nick Lewycky authored
Fixes PR9602! llvm-svn: 134665
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Eric Christopher authored
processor supports it just fine. Fixes PR9675 and rdar://9740801 llvm-svn: 134664
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Eric Christopher authored
Fixes PR10149 and rdar://9738585 llvm-svn: 134648
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- Jun 29, 2011
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Eric Christopher authored
via vectors. Part of rdar://9643582 llvm-svn: 134079
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- Jun 28, 2011
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Jakob Stoklund Olesen authored
Drop the FpMov instructions, use plain COPY instead. Drop the FpSET/GET instruction for accessing fixed stack positions. Instead use normal COPY to/from ST registers around inline assembly, and provide a single new FpPOP_RETVAL instruction that can access the return value(s) from a call. This is still necessary since you cannot tell from the CALL instruction alone if it returns anything on the FP stack. Teach fast isel to use this. This provides a much more robust way of handling fixed stack registers - we can tolerate arbitrary FP stack instructions inserted around calls and inline assembly. Live range splitting could sometimes break x87 code by inserting spill code in unfortunate places. As a bonus we handle floating point inline assembly correctly now. llvm-svn: 134018
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- Jun 25, 2011
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Chad Rosier authored
llvm-svn: 133874
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Chad Rosier authored
<rdar://problem/9483883> llvm-svn: 133858
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- Jun 24, 2011
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Chad Rosier authored
overheads. No functional change intended. llvm-svn: 133824
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- Jun 23, 2011
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Evan Cheng authored
llvm-svn: 133726
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- Jun 18, 2011
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Benjamin Kramer authored
llvm-svn: 133347
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- Jun 15, 2011
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John McCall authored
optimizations when emitting calls to the function; instead those calls may use faster relocations which require the function to be immediately resolved upon loading the dynamic object featuring the call. This is useful when it is known that the function will be called frequently and pervasively and therefore there is no merit in delaying binding of the function. Currently only implemented for x86-64, where it turns into a call through the global offset table. Patch by Dan Gohman, who assures me that he's going to add LangRef documentation for this once it's committed. llvm-svn: 133080
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- Jun 09, 2011
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Eric Christopher authored
No functional change. Part of PR6965 llvm-svn: 132763
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- Jun 07, 2011
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Stuart Hastings authored
load. rdar://problem/6373334 llvm-svn: 132696
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- Jun 04, 2011
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Stuart Hastings authored
rdar://problem/5993888 llvm-svn: 132606
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- Jun 03, 2011
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Eric Christopher authored
Part of rdar://9119939 llvm-svn: 132510
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- Jun 02, 2011
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Rafael Espindola authored
llvm-svn: 132479
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Stuart Hastings authored
rdar://problem/6373334 llvm-svn: 132458
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- Jun 01, 2011
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Stuart Hastings authored
floating-point comparison, generate a mask of 0s or 1s, and generally DTRT with NaNs. Only profitable when the user wants a materialized 0 or 1 at runtime. rdar://problem/5993888 llvm-svn: 132404
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Stuart Hastings authored
patch to TargetLowering.cpp. rdar://problem/5660695 llvm-svn: 132388
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- May 26, 2011
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Stuart Hastings authored
llvm-svn: 132108
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Stuart Hastings authored
rdar://problem/6920088 llvm-svn: 132105
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- May 24, 2011
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Evan Cheng authored
non-zero. - Teach X86 cmov optimization to eliminate the cmov from ctlz, cttz extension when the source of X86ISD::BSR / X86ISD::BSF is proven to be non-zero. rdar://9490949 llvm-svn: 131948
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- May 20, 2011
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Chad Rosier authored
llvm-svn: 131709
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- May 19, 2011
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Eric Christopher authored
Fixes rdar://9218925 Fixes PR9601 llvm-svn: 131682
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- May 18, 2011
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Chad Rosier authored
Enables vararg functions that pass all arguments via registers to be optimized into tail-calls when possible. llvm-svn: 131560
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- May 17, 2011
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Eli Friedman authored
llvm-svn: 131471
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