and let the ARMExpandPseudoInsts pass fix them up into the real (MOVs)
instruction form.

llvm-svn: 116534

pseudonym.

llvm-svn: 116512

llvm-svn: 116498

llvm-svn: 116488

creates a cyclic dependency that breaks the build when
BUILD_SHARED_LIBS=ON

llvm-svn: 116480

GEP + alloca.

llvm-svn: 116474

here. The f32 in FCONSTS is handled as a double instead of a float in the
code. So the encoding of the immediate into the instruction isn't exactly in
line with the documentation in that regard. But given that we know it's handled
as a double, it doesn't cause any harm.

llvm-svn: 116471

llvm-svn: 116466

- Add missing patterns for some multiply add/subtract instructions.
- Add encodings for VMRS and VMSR.

llvm-svn: 116464

llvm-svn: 116459

llvm-svn: 116454

llvm-svn: 116451

llvm-svn: 116450

llvm-svn: 116449

llvm-svn: 116447

llvm-svn: 116444

llvm-svn: 116440

llvm-svn: 116438

llvm-svn: 116437

and handle the operand explicitly. Flesh out encoding information. Add an
explicit disassembler testcase for the instruction.

llvm-svn: 116432

llvm-svn: 116431

llvm-svn: 116428

wfi, sel, sev and bkpt. All would disassemble properly before, but more
explicitness is good, especially with the integrated assembler coming in
the future.

llvm-svn: 116427

llvm-svn: 116421

llvm-svn: 116414

llvm-svn: 116412

immediates instead of 8 bits ones.

llvm-svn: 116410

8 bit constants can be used.

llvm-svn: 116403

llvm-svn: 116401

llvm-svn: 116389

just yet.

llvm-svn: 116386

llvm-svn: 116385

arithmetic-with-carry-in instructions.

llvm-svn: 116384

llvm-svn: 116383

llvm-svn: 116379

and move to a custom operand encoder. Remove the last of the special handling
stuff from ARMMCCodeEmitter::EncodeInstruction.

llvm-svn: 116377

llvm-svn: 116375

llvm-svn: 116370

Turn some fp stackifier assertion into errors to avoid silently generating bad code when assertions are off. rdar://8540457.

llvm-svn: 116368

explicit handling of the instructions referencing it from the MC code
emitter.

llvm-svn: 116367