llvm-svn: 6451

* ability to save BasicBlock references to be resolved later
* register remappings from the enum values to the real hardware numbers

llvm-svn: 6449

sections of instructions.

llvm-svn: 6448

For one, converting register numbers based on class in the code emitter.

llvm-svn: 6447

Code beautification for the rest of the code: changed layout to match the rest
of the code base.

llvm-svn: 6446

llvm-svn: 6444

broken up into their elements.  Too many programs break because of this.

llvm-svn: 6440

llvm-svn: 6439

behavior is technically undefined

llvm-svn: 6438

instructions of format 3.12 and 3.13 cannot inherit from F3rdrs1, because that
implies that the two registers are the first two parameters to the instruction.

Thus I made the instructions inherit from F3rd again, and manually added an rs1
field AFTER the shcnt field in the instruction, which maps to the appropriate
place in the instruction.

The other changes are just elimination of unnecessary spaces.

llvm-svn: 6437

internal phi nodes, and returns a new vector of basic blocks.

llvm-svn: 6431

SparcV9_F3.td: F3_12 and F3_13 instructions have rd and rs1 fields. Also,
 their fields were totally screwed up. This seems to fix the problem.

llvm-svn: 6429

llvm-svn: 6428

llvm-svn: 6425

llvm-svn: 6424

llvm-svn: 6423

llvm-svn: 6420

llvm-svn: 6415

llvm-svn: 6411

has their path set up by this point.

llvm-svn: 6410

llvm-svn: 6403

llvm-svn: 6397

* Make the function inliner _significantly_ smarter.  :)

llvm-svn: 6396

exit code. This, in turn, makes an empty file SparcV9CodeEmitter.inc, and only
much later, produces a link error because the key function that TableGen creates
isn't found.

Using a temporary file in the middle forces a good .INC file to be generated by
TableGen, and it will keep trying until you fix the input file.

llvm-svn: 6392

llvm-svn: 6390

Also, added a rule to delete the generated .inc file on `make clean'.

llvm-svn: 6389

* Added some Format 4 classes, but not instructions
* Added notes on missing sections with FIXMEs
* Added RDCCR instr

llvm-svn: 6388

llvm-svn: 6387

llvm-svn: 6385

list (rd, rs1, imm), in that order (bit-wise), the actual assembly syntax is
instr rd, imm, rs1, and that is how they are constructed in the instruction
selector. This fixes the discrepancy.

Also fixed some comments along the same lines and fixed page numbers referring
to where instructions are described in the Sparc manual.

llvm-svn: 6384

llvm-svn: 6383

llvm-svn: 6381

changed.

llvm-svn: 6380

and passes the real code to a memory-outputting code emitter. This may be
removed at a later point in development.

llvm-svn: 6379

MachineInstr can later be patched up correctly.

llvm-svn: 6378

llvm-svn: 6377

Non-obvious change: since I have changed ST and STD to be STF and STDF to
(a) closer resemble their name (NOT assembly text) in the Sparc manual, and
(b) clearly specify that they they are floating-point opcodes,
I made the same changes in this file.

llvm-svn: 6376

Here I had to make one non-trivial change: add a function to get a version of
the opcode that takes an immediate, given an opcode that takes all registers.

This is required because sometimes it is not known at construction time which
opcode is used because opcodes are passed around between functions.

llvm-svn: 6375

llvm-svn: 6373

llvm-svn: 6372