llvm-svn: 55468

If a copy isn't coalesced, but its src is defined by trivial computation. Re-materialize the src to replace the copy.

llvm-svn: 55467

llvm-svn: 55466

llvm-svn: 55465

llvm-svn: 55463

llvm-svn: 55462

 - Added ASTContext::getObjCEncodingForPropertyDecl.

llvm-svn: 55461

for operands: rdar://6179606.  no testcase, because I can't write
a .ll file that is this broken ;-)

llvm-svn: 55460

Cleanup ubigraph files when don't drawing the graphs.

llvm-svn: 55459

Prakash Prabhu!

llvm-svn: 55458

ATOMIC_LOAD_ADD_{8,16,32,64} instead of ATOMIC_LOAD_ADD.
Increased the Hardcoded Constant OpActionsCapacity to match.
Large but boring; no functional change.

This is to support partial-word atomics on ppc; i8 is
not a valid type there, so by the time we get to lowering, the
ATOMIC_LOAD nodes looks the same whether the type was i8 or i32.
The information can be added to the AtomicSDNode, but that is the
largest SDNode; I don't fully understand the SDNode allocation,
but it is sensitive to the largest node size, so increasing
that must be bad.  This is the alternative.

llvm-svn: 55457

Feel free to fix a better way!

llvm-svn: 55456

llvm-svn: 55455

llvm-svn: 55452

llvm-svn: 55451

works with.

SelectionDAG, FunctionLoweringInfo, and SelectionDAGLowering
objects now get created once per SelectionDAGISel instance, and
can be reused across blocks and across functions. Previously,
they were created and destroyed each time they were needed.

This reorganization simplifies the handling of PHI nodes, and
also SwitchCases, JumpTables, and BitTestBlocks. This
simplification has the side effect of fixing a bug in FastISel
where successor PHI nodes weren't being updated correctly.

This is also a step towards making the transition from FastISel
into and out of SelectionDAG faster, and also making
plain SelectionDAG faster on code with lots of little blocks.

llvm-svn: 55450

llvm-svn: 55449

llvm-svn: 55448

llvm-svn: 55447

llvm-svn: 55446

llvm-svn: 55442

llvm-svn: 55441

llvm-svn: 55440

llvm-svn: 55439

SSE2 registers as well as the MMX registers.

llvm-svn: 55436

llvm" for consistency.

llvm-svn: 55435

llvm-svn: 55434

llvm-svn: 55433

llvm-svn: 55432

llvm-svn: 55431

llvm-svn: 55430

llvm-svn: 55429

Use TargetLowering to get the types in fast isel, which handles pointer types correctly for our purposes.

llvm-svn: 55428

just try to do the action and let the tablegen-generated code
determine if there is target-support for an operation.

llvm-svn: 55427

the details of materializing constants and other values into
registers, and make use of it in several places.

llvm-svn: 55426

llvm-svn: 55425

llvm-svn: 55424

llvm-svn: 55423

64-bit registers from 16-bit and smaller memory locations, prefer
instructions that define the entire 64-bit register, to avoid
partial-register updates.

llvm-svn: 55422

of two, and to not need a scratch std::vector. Also, compute the ordering
immediately in the result array, instead of in another scratch std::vector
that is copied to the result array.

llvm-svn: 55421