llvm-svn: 128820

llvm-svn: 128818

llvm-svn: 128812

returning a scalar value in a function whose return type is a single-
element structure or array.

llvm-svn: 128810

Contributed by: etherzhhb@gmail.com

llvm-svn: 128808

ref_cnt mutable and Retain/Release const to enable reference counted
pointers to const objects

llvm-svn: 128804

llvm-commits.  (Not sure why it only breaks on Windows; maybe it has
something to do with the iterator representation...)

llvm-svn: 128802

separate executable.

llvm-svn: 128801

llvm-svn: 128800

 - Adds support for sniffing PE/COFF files on win32 (.exe and .dll)
   which are COFF files that have an MS-DOS compatibility stub on
   the front of them.

 - Fixes a bug in the COFFObjectFile's support for the Microsoft COFF
   extension for long symbol names, wherein it was attempting to parse
   the leading '/' in an extended symbol name reference as part of the
   integer offset.

 - Fixes bugs in COFFObjectFile and ELFObjectFile wherein section
   and symbol iterators were being returned with uninitialized bytes;
   the type DataRefImpl is a union between 2 32-bit words (d.a and d.b)
   and a single intptr_t word (p). Only p was being initialized, so in
   32-bit builds the result would be iterators with random upper 32-bit
   words in their DataRefImpls. This caused random failures when
   seeking around in object files.

Patch by Graydon Hoare!

llvm-svn: 128799

Patch by Patrick Walton!

llvm-svn: 128798

Remove the LLVMContext& arguments from *Folder constructors, as they don't seem to be used anywhere.

llvm-svn: 128793

Patch by arrowdodger!

llvm-svn: 128789

after the given instruction; make sure to handle that case correctly.
(It's difficult to trigger; the included testcase involves a dead 
block, but I don't think that's a requirement.) 

While I'm here, get rid of the unnecessary warning about
SimplifyInstructionsInBlock, since it should work correctly as far as I know.

llvm-svn: 128782

Based on PR9429, but no testcase because I can't figure out how to trigger it
anymore given other changes to the relevant code.

llvm-svn: 128781

It's possible to craft an input that hits the recursion limits in a way
that SimplifyDemandedBits doesn't simplify the icmp but ComputeMaskedBits
can infer which bits are zero.

No test case as it depends on too many other things. Fixes PR9609.

llvm-svn: 128777

If someone first configure build with LLVM_ENABLE_FFI=1 and then turn it
off, the build will fail in lib/ExecutionEngine/Interpreter because
Interpreter will try still to #include <ffi/ffi.h>, but there are no
include_directories(${FFI_INCLUDE_DIR}) now.

This patch unset()'s HAVE_FFI_H and HAVE_FFI_FFI_H from cache file if
LLVM_ENABLE_FFI=0. This forces CMake to update config.h.

Patch by arrowdodger!

llvm-svn: 128769

llvm-svn: 128767

llvm-svn: 128765

When the greedy register allocator is splitting multiple global live ranges, it
tends to look at the same interference data many times. The InterferenceCache
class caches queries for unaltered LiveIntervalUnions.

llvm-svn: 128764

This is more compact and faster than using DenseMap.

llvm-svn: 128763

registers that arise from argument shuffling with the soft float ABI. These
instructions are particularly slow on Cortex A8. This fixes one half of
<rdar://problem/8674845>.

llvm-svn: 128759

transformations in target-specific DAG combines without causing DAGCombiner to
delete the same node twice. If you know of a better way to avoid this (see my
next patch for an example), please let me know.

llvm-svn: 128758

instead of the second operand in addrmode_imm12.

rdar://problem/9225289

llvm-svn: 128757

llvm-svn: 128751

llvm-svn: 128750

rdar://problem/9224276

llvm-svn: 128749

rdar://problem/9224120

llvm-svn: 128748

all the instruction have:

    let Inst{31-27} = 0b1110; // non-predicated

Before, the ARM decoder was confusing:

> 0x40 0xf3 0xb8 0x80

as:

Opcode=16 Name=ADCSSrs Format=ARM_FORMAT_DPSOREGFRM(5)
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0 
-------------------------------------------------------------------------------------------------
| 1: 0: 0: 0| 0: 0: 0: 0| 1: 0: 1: 1| 1: 0: 0: 0| 1: 1: 1: 1| 0: 0: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0|
-------------------------------------------------------------------------------------------------

	adcs	pc, r8, r0, asr #6

since the cond field for ADCSSrs is a wild card, and so is ADCrs, with the ADCSSrs having Inst{20} as '1'.

Now, the AR decoder behaves correctly:

> 0x40 0xf3 0xb8 0x80
> END
Executing command: /Volumes/data/lldb/llvm/Debug+Asserts/bin/llvm-mc -disassemble -triple=arm-apple-darwin -debug-only=arm-disassembler mc-input.txt

Opcode=19 Name=ADCrs Format=ARM_FORMAT_DPSOREGFRM(5)
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0 
-------------------------------------------------------------------------------------------------
| 1: 0: 0: 0| 0: 0: 0: 0| 1: 0: 1: 1| 1: 0: 0: 0| 1: 1: 1: 1| 0: 0: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0|
-------------------------------------------------------------------------------------------------

	adcshi	pc, r8, r0, asr #6
> 

rdar://problem/9223094

llvm-svn: 128746

llvm-svn: 128745

- Localize the check if an icmp has one use to a place where we know we're
  introducing something that's likely more expensive than a sext from i1.
- Add an assert to make sure a case that would lead to a miscompilation is
  folded away earlier.
- Fix a typo.

llvm-svn: 128744

llvm-svn: 128743

Remove redundant code. There are assignments to variables Base and Offset right after the code that is removed.

llvm-svn: 128742

llvm-svn: 128741

llvm-svn: 128740

When the architecture is explicitly armv6 or thumbv6, we need to mark the object file appropriately.

llvm-svn: 128739

llvm-svn: 128736

llvm-svn: 128735

Fix a LDRT/LDRBT decoding bug where for Encoding A2, if Inst{4} != 0, we should reject the instruction
as invalid.

llvm-svn: 128734

llvm-svn: 128733