llvm-svn: 23732

llvm-svn: 23731

type constraint.  This lets tblgen realize that it doesn't need any dynamic
type checks for fextend/fround on PPC (and many other targets), because there
are only two fp types.

llvm-svn: 23730

Overall, no functionality change yet though.

llvm-svn: 23729

llvm-svn: 23728

llvm-svn: 23727

llvm-svn: 23726

llvm-svn: 23725

1. If an operation has to be int or fp and the target only supports one
   int or fp type, relize that the op has to have that type.
2. If a target has operations on multiple types, do not emit matching code
   for patterns involving those operators, since we do not emit the code to
   check for them yet.  This prevents PPC from generating FP ops currently.

Also move some code around into more logical places.

llvm-svn: 23724

llvm-svn: 23723

popping up in Fourinarow.

llvm-svn: 23722

llvm-svn: 23721

you could be AND'ing with the result of a shift that shifts out all the
bits you care about, in addition to a constant.

Also, move over an add/sub_parts fold from legalize to the dag combiner,
where it works for things other than constants.  Woot!

llvm-svn: 23720

llvm-svn: 23719

llvm-svn: 23718

llvm-svn: 23717

is also legal.  Add support for ExpandOp'ing raw EXTLOADs too.

llvm-svn: 23716

llvm-svn: 23715

the remainder of the failures introduced by my patch last night.

llvm-svn: 23714

tests.

llvm-svn: 23713

llvm-svn: 23712

parts. This should fix the crafty and signed long long unit test failure
on x86 last night.

llvm-svn: 23711

minimize unnecessary spilling.

llvm-svn: 23710

llvm-svn: 23709

edges associated with said node from the dot files produced by
DSA.

llvm-svn: 23708

llvm-svn: 23707

Kill some dead code.

llvm-svn: 23706

llvm-svn: 23705

out, where after the first CombineTo() call, the node the second CombineTo
wishes to replace may no longer exist.

Fix a very real bug with the truncated load optimization on little endian
targets, which do not need a byte offset added to the load.

llvm-svn: 23704

like turning:

_foo:
        fctiwz f0, f1
        stfd f0, -8(r1)
        lwz r2, -4(r1)
        rlwinm r3, r2, 0, 16, 31
        blr

into
_foo:
        fctiwz f0,f1
        stfd f0,-8(r1)
        lhz r3,-2(r1)
        blr

Also removed an unncessary constraint from sra -> srl conversion, which
should take care of hte only reason we would ever need to handle sra in
MaskedValueIsZero, AFAIK.

llvm-svn: 23703

llvm-svn: 23702

llvm-svn: 23700

llvm-svn: 23699

out CSE's of base expressions it could build a result whose order was
nondet.

llvm-svn: 23698

from the end of a vector instead of the beginning

llvm-svn: 23697

llvm-svn: 23696

llvm-svn: 23695

llvm-svn: 23694

llvm-svn: 23693

llvm-svn: 23692