llvm-svn: 108679

TblGen/AsmMatcher: Add support for honoring instruction Requires<[]> attributes as part of the matcher.
 - Currently includes a hack to limit ourselves to "In32BitMode" and "In64BitMode", because we don't have the other infrastructure to properly deal with setting SSE, etc. features on X86.

llvm-svn: 108677

 - Unfortunate, but necessary for now to handle subtarget instruction matching. Eventually we should factor out the lower level target machine information so we don't need to do this.

llvm-svn: 108664

llvm-svn: 108626

llvm-svn: 108625

llvm-svn: 108588

needsStackRealignment is currently checking the can conditions as well.

llvm-svn: 108581

llvm-svn: 108567

llvm-svn: 108565

thus is a much more meaningful name.

llvm-svn: 108563

The isLive() method can read uninitialized memory, but it still gives correct
results.

llvm-svn: 108561

llvm-svn: 108545

pass that inserted it.

It is no longer necessary to limit the live ranges of FP registers to a single
basic block.

llvm-svn: 108536

llvm-svn: 108535

FP_REG_KILL instructions are still inserted, but can be disabled by passing
-live-x87 to llc. The X87FPRegKillInserterPass is going to be removed shortly.

CFG edges are partioned into bundles where the x87 stack must be allocated
identically. Code is insertad at the end of each basic block that shuffles the
live FP registers to match the outgoing bundles expectations.

This fix is in preparation for some upcoming register allocator improvements
that may extend the live range of registers beyond a basic block, similar to
LICM. It also provides a nice runtime speedup if you are building with
-mfpmath=387.

llvm-svn: 108529

-enable-no-nans-fp-math and -enable-no-infs-fp-math. All of the current codegen fp math optimizations only care whether the fp arithmetics arguments and results can never be NaN.

llvm-svn: 108465

this fixes rdar://8192860.  Unfortunately it can only be triggered
with llc because llvm-mc matches another (correctly encoded) version
of this, so no testcase.

llvm-svn: 108454

llvm-svn: 108387

lowering atomics. This will allow those copies to still be coalesced after
TII::isMoveInstr is removed.

llvm-svn: 108385

llvm-svn: 108368

llvm-svn: 108366

patch by Michael Spencer!

llvm-svn: 108342

address cannot be allocated a register is in 32-bit mode where the first
three arguments are marked inreg. In that case EAX, EDX, and ECX will be
used for argument passing.

This fixes PR7610.

llvm-svn: 108327

constants, since they may not be emited near the other instructions
which get the same line, and this confuses debug info.

llvm-svn: 108302

llvm-svn: 108286

Add the x86 VEX_L form to handle special cases where VEX_L must be set.

llvm-svn: 108274

llvm-svn: 108265

disassembler.  Remove some code from the disassembler to
compensate, unbreaking disassembly of lea's.

llvm-svn: 108226

llvm-svn: 108224

llvm-svn: 108223

llvm-svn: 108222

Move some SIMD fragment code into X86InstrFragmentsSIMD so that the
utility classes can be used from multiple files.  This will aid
transitioning to a new refactored x86 SIMD specification.

llvm-svn: 108213

llvm-svn: 108207

llvm-svn: 108204

SD instructions too, in addition to SS instructions. And
add a comment about it.

llvm-svn: 108191

llvm-svn: 108184

llvm-svn: 108167

support branching on x87 comparisons yet. This fixes PR7624.

llvm-svn: 108149

llvm-svn: 108123

This fixes PR7375.

llvm-svn: 108120